Invention Grant
- Patent Title: Semiconductor structure with a laminated layer
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Application No.: US17646901Application Date: 2022-01-04
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Publication No.: US11978669B2Publication Date: 2024-05-07
- Inventor: Chia-Lin Chuang , Chia-Hao Chang , Sheng-Tsung Wang , Lin-Yu Huang , Tien-Lu Lin , Yu-Ming Lin , Chih-Hao Wang
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- The original application number of the division: US16656384 2019.10.17
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/522 ; H01L23/528

Abstract:
The present disclosure provides a semiconductor structure. The structure includes a semiconductor substrate, a gate stack over a first portion of a top surface of the semiconductor substrate; and a laminated dielectric layer over at least a portion of a top surface of the gate stack. The laminated dielectric layer includes at least a first sublayer and a second sublayer. The first sublayer is formed of a material having a dielectric constant lower than a dielectric constant of a material used to form the second sublayer and the material used to form the second sublayer has an etch selectivity higher than an etch selectivity of the material used to form the first sublayer.
Public/Granted literature
- US20220181206A1 SEMICONDUCTOR STRUCTURE WITH A LAMINATED LAYER Public/Granted day:2022-06-09
Information query
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