公开(公告)号：US12002709B2

公开(公告)日：2024-06-04

申请号：US17459961

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Wei Liu ,  Wei-Chen Chu ,  Chia-Tien Wu ,  Tai-I Yang

IPC: H01L29/40 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/027

CPC classification number: H01L21/76807 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L21/0276 ,  H01L21/31116

Abstract: The present disclosure provides an interconnect structure, including a first metal line, a second metal line spaced away from the first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, wherein a shortest distance between the second portion and the second metal line is in a range from 50 Angstrom to 200 Angstrom, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, the entire first portion and the entire second portion are under a coverage of a vertical projection area of the third portion, a first layer, and a second layer over the first layer.

公开(公告)号：US09716035B2

公开(公告)日：2017-07-25

申请号：US14310618

申请日：2014-06-20

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-I Yang ,  Yung-Chih Wang ,  Cheng-Chi Chuang ,  Chia-Tien Wu ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76877 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76885 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An embodiment semiconductor device includes a substrate and a dielectric layer over the substrate. The dielectric layer includes a first conductive line and a second conductive line. The second conductive line comprises a different conductive material than the first conductive line.

公开(公告)号：US09558986B2

公开(公告)日：2017-01-31

申请号：US14030156

申请日：2013-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tai-I Yang ,  Hong-Seng Shue ,  Kun-Ming Huang ,  Chih-Heng Shen ,  Po-Tao Chu

IPC: H01L21/26 ,  H01L29/16 ,  H01L21/00 ,  H01L29/06 ,  H01L21/76 ,  H01L21/762 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L29/0634 ,  H01L29/78

Abstract: A semiconductor structure includes a semiconductor substrate, a first doped region, a second doped region and a dielectric. The first doped region and the second doped region respectively has an aspect ratio and a dopant concentration uniformity along a depth in the semiconductor substrate. The dielectric is between the first doped region and the second doped region. The dopant concentration uniformity is within 0.2% and the aspect ratio of the semiconductor substrate is greater than about 10.

Abstract translation: 半导体结构包括半导体衬底，第一掺杂区，第二掺杂区和电介质。 第一掺杂区域和第二掺杂区域分别具有沿半导体衬底的深度的纵横比和掺杂剂浓度均匀性。 电介质位于第一掺杂区和第二掺杂区之间。 掺杂剂浓度均匀度在0.2％以内，半导体衬底的纵横比大于约10。

公开(公告)号：US20160358817A1

公开(公告)日：2016-12-08

申请号：US15243572

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-I Yang ,  Hsiang-Wei Liu ,  Chia-Tien Wu ,  Hsiang-Huan Lee ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76843

Abstract: Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.

Abstract translation: 公开了导电元件结构及其制造方法。 在一些实施例中，在绝缘层中形成导电元件的方法包括：在设置在绝缘层上的金属层中形成凹陷; 在所述凹部的侧壁上选择性地形成金属衬垫; 并使用金属层和金属衬垫作为掩模在绝缘层中蚀刻通孔。

公开(公告)号：US20160020168A1

公开(公告)日：2016-01-21

申请号：US14334929

申请日：2014-07-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Lun Kao ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Jian-Hua Chen ,  Yu-Chieh Liao ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L21/263 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/2633 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device comprises a first rounded metal line in a metallization layer over a substrate, a second rounded metal line in the metallization layer, a first air gap between sidewalls of the first rounded metal line and the second metal line, a first metal line in the metallization layer, wherein a top surface of the first metal line is higher than a top surface of the second rounded metal line and a bottom surface of the first metal line is substantially level with a bottom surface of the second rounded metal line and a second air gap between sidewalls of the second rounded metal line and the first metal line.

Abstract translation: 器件包括在衬底上的金属化层中的第一圆形金属线，金属化层中的第二圆形金属线，第一圆形金属线的侧壁与第二金属线之间的第一气隙， 金属化层，其中第一金属线的顶表面高于第二圆形金属线的顶表面，并且第一金属线的底表面基本上与第二圆形金属线的底表面平齐，第二空气 第二圆形金属线的侧壁与第一金属线之间的间隙。

公开(公告)号：US20150380303A1

公开(公告)日：2015-12-31

申请号：US14319464

申请日：2014-06-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-I Yang ,  Hsiang-Wei Liu ,  Chia-Tien Wu ,  Hsiang-Huan Lee ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/76877 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76843

Abstract: Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.

Abstract translation: 公开了导电元件结构及其制造方法。 在一些实施例中，在绝缘层中形成导电元件的方法包括：在设置在绝缘层上的金属层中形成凹陷; 在所述凹部的侧壁上选择性地形成金属衬垫; 并使用金属层和金属衬垫作为掩模在绝缘层中蚀刻通孔。

公开(公告)号：US20220367357A1

公开(公告)日：2022-11-17

申请号：US17874381

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first interconnect arranged within an inter-level dielectric (ILD) layer. The first interconnect has opposing sidewalls that are both laterally separated from closest neighboring interconnects within the ILD layer by one or more air-gaps along a cross-sectional view. A second interconnect is arranged within the ILD layer. The ILD layer laterally contacts opposing sidewalls of the second interconnect as viewed along the cross-sectional view.

公开(公告)号：US09735232B2

公开(公告)日：2017-08-15

申请号：US14339974

申请日：2014-07-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Tai-I Yang ,  Jheng-Sheng You ,  Chi-Fu Lin ,  Tien-Lu Lin

IPC: H01L29/06 ,  H01L29/78

CPC classification number: H01L29/0661 ,  H01L29/0634 ,  H01L29/78

Abstract: The present disclosure provides a method for manufacturing a semiconductor structure. The method includes several operations as follows. A semiconductor substrate is received. A trench along a depth in the semiconductor substrate is formed. The semiconductor substrate is exposed in a hydrogen containing atmosphere. Dopants are inserted into a portion of the semiconductor substrate. A dielectric is filled in the trench. The dopants are driven into a predetermined distance in the semiconductor substrate.

公开(公告)号：US20170162504A1

公开(公告)日：2017-06-08

申请号：US15442282

申请日：2017-02-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Lun Kao ,  Hsiang-Wei Liu ,  Tai-I Yang ,  Jian-Hua Chen ,  Yu-Chieh Liao ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/263 ,  H01L21/311

CPC classification number: H01L23/5283 ,  H01L21/2633 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method comprises forming a first conductive line and a second conductive line in a first dielectric layer over a substrate, each having a planar top surface, applying an etch-back process to the first dielectric layer until a dielectric portion between the first conductive line and the second conductive line has been removed, and the first conductive line and the second conductive line have respective cross sectional shapes including a rounded surface and two rounded corners and depositing a second dielectric layer over the substrate, while leaving a first air gap between the first conductive line and the second conductive line.

公开(公告)号：US09595471B2

公开(公告)日：2017-03-14

申请号：US15243572

申请日：2016-08-22

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tai-I Yang ,  Hsiang-Wei Liu ,  Chia-Tien Wu ,  Hsiang-Huan Lee ,  Tien-Lu Lin

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3105

CPC classification number: H01L21/76877 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02244 ,  H01L21/02258 ,  H01L21/0337 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32133 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76843

Abstract: Conductive element structures and methods of manufacture thereof are disclosed. In some embodiments, a method of forming a conductive element in an insulating layer includes: forming a recess in a metal layer disposed over the insulating layer; selectively forming a metal liner on a sidewall of the recess; and etching a via in the insulating layer using the metal layer and the metal liner as a mask.

Abstract translation: 公开了导电元件结构及其制造方法。 在一些实施例中，在绝缘层中形成导电元件的方法包括：在设置在绝缘层上的金属层中形成凹陷; 在所述凹部的侧壁上选择性地形成金属衬垫; 并使用金属层和金属衬垫作为掩模在绝缘层中蚀刻通孔。