公开(公告)号：US12094816B2

公开(公告)日：2024-09-17

申请号：US17460859

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Chen Chu ,  Chia-Tien Wu ,  Chia-Wei Su ,  Yu-Chieh Liao ,  Chia-Chen Lee ,  Hsin-Ping Chen ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.

公开(公告)号：US12183671B2

公开(公告)日：2024-12-31

申请号：US18313480

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pokuan Ho ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Wei-Chen Chu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.

公开(公告)号：US12002709B2

公开(公告)日：2024-06-04

申请号：US17459961

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Wei Liu ,  Wei-Chen Chu ,  Chia-Tien Wu ,  Tai-I Yang

IPC: H01L29/40 ,  H01L21/311 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/027

CPC classification number: H01L21/76807 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L21/0276 ,  H01L21/31116

Abstract: The present disclosure provides an interconnect structure, including a first metal line, a second metal line spaced away from the first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, wherein a shortest distance between the second portion and the second metal line is in a range from 50 Angstrom to 200 Angstrom, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, the entire first portion and the entire second portion are under a coverage of a vertical projection area of the third portion, a first layer, and a second layer over the first layer.

公开(公告)号：US10734275B2

公开(公告)日：2020-08-04

申请号：US16727593

申请日：2019-12-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Wei Liu ,  Chia-Tien Wu ,  Wei-Chen Chu

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/3115 ,  H01L21/311

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

公开(公告)号：US20200144104A1

公开(公告)日：2020-05-07

申请号：US16727593

申请日：2019-12-26

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsiang-Wei Liu ,  Chia-Tien Wu ,  Wei-Chen Chu

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3115

Abstract: A method includes forming a hard mask over a target layer, performing a treatment on a first portion of the hard mask to form a treated portion, with a second portion of the hard mask left untreated as an untreated portion. The method further includes subjecting both the treated portion and the untreated portion of the hard mask to etching, in which the untreated portion is removed as a result of the etching, and the treated portion remains after the etching. A layer underlying the hard mask is etched, and the treated portion of the hard mask is used as a part of an etching mask in the etching.

公开(公告)号：US20230282571A1

公开(公告)日：2023-09-07

申请号：US18313480

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pokuan Ho ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Wei-Chen Chu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528

Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.

公开(公告)号：US20230275018A1

公开(公告)日：2023-08-31

申请号：US17832584

申请日：2022-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Tien Wu ,  Wei-Chen Chu ,  Yu-Chieh Liao ,  Hsin-Ping Chen

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11 ,  G11C11/417 ,  G11C11/412

CPC classification number: H01L23/5226 ,  H01L21/76877 ,  H01L21/76816 ,  H01L23/528 ,  H01L21/76831 ,  H01L23/53252 ,  H01L27/1104 ,  G11C11/417 ,  G11C11/412

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a first interconnect layer over a substrate, the first interconnect layer including a first conductive feature and a second conductive feature, forming a patterned mask on the first interconnect layer, one or more openings in the patterned mask overlaying the second conductive feature, recessing the second conductive feature through the one or more openings in the patterned mask, and forming a second interconnect layer over the first interconnect layer. The second interconnect layer includes a first via in contact with the first conductive feature and a second via in contact with the second conductive feature.

公开(公告)号：US11729969B1

公开(公告)日：2023-08-15

申请号：US17672053

申请日：2022-02-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Wei Liu ,  Wei-Chen Chu ,  Chia-Tien Wu

IPC: G11C17/16 ,  H10B20/20 ,  H01L23/525 ,  G11C17/18

CPC classification number: H10B20/20 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5256

Abstract: A semiconductor device and a method of operating the same are provided. The semiconductor device includes a transistor and a fuse structure electrically connected to the transistor. The fuse structure includes a first fuse element, a second fuse element, and a fuse medium. The second fuse element at least partially overlaps the first fuse element. The fuse medium connects the first fuse element and the second fuse element. The fuse medium includes an electrically conductive material.

公开(公告)号：US11107725B2

公开(公告)日：2021-08-31

申请号：US17026294

申请日：2020-09-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Wei Liu ,  Wei-Chen Chu ,  Chia-Tien Wu ,  Tai-I Yang

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/027

Abstract: The present disclosure provides an interconnect structure, including a first metal line, a conductive contact over the first metal line, including a first portion, a second portion over the first portion, wherein a bottom width of the second portion is greater than a top width of the first portion, and a third portion over the second portion, wherein a bottom width of the third portion is greater than a top width of the second portion, a sacrificial bilayer, including a first sacrificial layer, wherein a first portion of the first sacrificial layer is under a coverage of a vertical projection area of the first portion of the conductive contact, and a second sacrificial layer over the first sacrificial layer, and a dielectric layer over a top surface of the second sacrificial layer.

公开(公告)号：US10784151B2

公开(公告)日：2020-09-22

申请号：US16128031

申请日：2018-09-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Hsiang-Wei Liu ,  Wei-Chen Chu ,  Chia-Tien Wu ,  Tai-I Yang

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/027

Abstract: The present disclosure provides a method for forming an interconnect structure, including forming an Nth metal line principally extending in a first direction, forming a sacrificial bilayer over the Nth metal line, forming a dielectric layer over the sacrificial bilayer, removing a portion of the sacrificial bilayer, forming a conductive post in the sacrificial bilayer, wherein the conductive post having a top pattern coplanar with a top surface of the sacrificial bilayer and a bottom pattern in contact with a top surface of the Nth metal line, and forming an Nth metal via over the sacrificial bilayer.