公开(公告)号：US12094816B2

公开(公告)日：2024-09-17

申请号：US17460859

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Wei-Chen Chu ,  Chia-Tien Wu ,  Chia-Wei Su ,  Yu-Chieh Liao ,  Chia-Chen Lee ,  Hsin-Ping Chen ,  Shau-Lin Shue

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329

Abstract: A semiconductor structure includes a substrate, a dielectric layer, a first conductive feature and a second conductive feature. The substrate includes a semiconductor device. The dielectric layer is disposed on the substrate. The first conductive feature is formed in the first dielectric layer. The second conductive feature penetrates the first conductive feature and the dielectric layer, and is electrically connected to the first conductive feature and the semiconductor device.

公开(公告)号：US11923306B2

公开(公告)日：2024-03-05

申请号：US17461152

申请日：2021-08-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chia-Wei Su ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Shau-Lin Shue

IPC: H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/31133 ,  H01L21/7682 ,  H01L21/76832 ,  H01L23/5283

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling a conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.

公开(公告)号：US11923273B2

公开(公告)日：2024-03-05

申请号：US17816327

申请日：2022-07-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Shih-Wei Peng ,  Chia-Tien Wu ,  Jiann-Tyng Tzeng

IPC: H01L23/48 ,  H01L21/48

CPC classification number: H01L23/481 ,  H01L21/4828

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of first metal strips extending in a first direction on a first plane; and forming a plurality of second metal strips extending in the first direction on a second plane over the first plane by executing a photolithography operation with a single mask, wherein a first second metal strip (FIG. 1, 131) is disposed over a first first metal strip; wherein the first first metal strip and the first second metal strip are directed to a first voltage source; wherein a distance between the first second metal strip and a second second metal strip immediate adjacent to the first second metal strip is greater than a distance between the second second metal strip and a third second metal strip immediate adjacent to the second second metal strip.

公开(公告)号：US20230369231A1

公开(公告)日：2023-11-16

申请号：US18360066

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Yen Huang ,  Chia-Tien Wu

IPC: H01L23/538 ,  H01L21/768 ,  H01L21/48 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/76802 ,  H01L21/486 ,  H01L23/5386 ,  H01L21/7682 ,  H01L23/5329

Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

公开(公告)号：US20220336360A1

公开(公告)日：2022-10-20

申请号：US17543518

申请日：2021-12-06

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shih-Wei Peng ,  Chia-Tien Wu ,  Jiann-Tyng Tzeng

IPC: H01L23/538 ,  H01L21/768

Abstract: A semiconductor structure including a first conductive layer, a second conductive layer situated above the first conductive layer, and a via extending diagonally between the second conductive layer and the first conductive layer to electrically connect the first conductive layer to the second conductive layer.

公开(公告)号：US10163654B2

公开(公告)日：2018-12-25

申请号：US15237898

申请日：2016-08-16

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yung-Sung Yen ,  Chung-Ju Lee ,  Chun-Kuang Chen ,  Chia-Tien Wu ,  Ta-Ching Yu ,  Kuei-Shun Chen ,  Ru-Gun Liu ,  Shau-Lin Shue ,  Tsai-Sheng Gau ,  Yung-Hsu Wu

IPC: H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L21/033 ,  H01L21/8238 ,  H01L21/8234

Abstract: A method includes forming a material layer over a substrate, forming a first hard mask (HM) layer over the material layer, forming a first trench, along a first direction, in the first HM layer. The method also includes forming first spacers along sidewalls of the first trench, forming a second trench in the first HM layer parallel to the first trench, by using the first spacers to guard the first trench. The method also includes etching the material layer through the first trench and the second trench, removing the first HM layer and the first spacers, forming a second HM layer over the material layer, forming a third trench in the second HM layer. The third trench extends along a second direction that is perpendicular to the first direction and overlaps with the first trench. The method also includes etching the material layer through the third trench.

公开(公告)号：US10162930B2

公开(公告)日：2018-12-25

申请号：US15229536

申请日：2016-08-05

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Wei-Cheng Lin ,  Kam-Tou Sio ,  Shih-Wei Peng ,  Hui-Ting Yang′ ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chew-Yuen Young ,  Chia-Tien Wu ,  Chih-Ming Lai

IPC: G06F17/50

Abstract: A method performed by at least one processor comprises the operations of obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form, determining a unit pattern having a width of n times of the gate pitch, assigning m consecutive metal lines to the unit pattern, dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R), determining an integer P so that a value of the remainder R divided by P satisfies a layout precision, and determining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P.

公开(公告)号：US09490136B1

公开(公告)日：2016-11-08

申请号：US14840199

申请日：2015-08-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yu-Sheng Chang ,  Chia-Tien Wu ,  Yung-Hsu Wu

IPC: H01L21/308

CPC classification number: H01L21/0337

Abstract: A method includes forming a hard mask (HM) stack over a material layer, which has a first, second, third and fourth HM layers. The method also includes forming a first trench in the fourth HM layer, forming a first spacer in the first trench, forming a second trench in the fourth HM layer, removing at least a portion of the first spacer to form a cut by using the third HM layer as an etch-stop layer, removing a portion of the third HM layer and the second HM layer exposed by the first trench, second trench, and cut to form an extended first trench, extended second trench, and extended cut, respectively. The method also includes forming second spacers in the extended first trench, the extended second trench, and the extended cut and removing another portion of the second HM layer to form a third trench.

Abstract translation: 一种方法包括在具有第一，第二，第三和第四HM层的材料层上形成硬掩模（HM）堆叠。 该方法还包括在第四HM层中形成第一沟槽，在第一沟槽中形成第一间隔物，在第四HM层中形成第二沟槽，通过使用第三HM层去除第一间隔物的至少一部分以形成切口 HM层作为蚀刻停止层，去除由第一沟槽，第二沟槽和切口暴露的第三HM层的一部分和第二HM层，以分别形成延伸的第一沟槽，延伸的第二沟槽和延伸的切口。 该方法还包括在延伸的第一沟槽，延伸的第二沟槽和延伸的切口中形成第二间隔物，并且移除第二HM层的另一部分以形成第三沟槽。

公开(公告)号：US12125795B2

公开(公告)日：2024-10-22

申请号：US18360066

申请日：2023-07-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsin-Chieh Yao ,  Chung-Ju Lee ,  Chih Wei Lu ,  Hsi-Wen Tien ,  Wei-Hao Liao ,  Yu-Teng Dai ,  Hsin-Yen Huang ,  Chia-Tien Wu

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5384 ,  H01L21/486 ,  H01L21/76802 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/5386

Abstract: The present disclosure relates to an integrated chip comprising a substrate. A first conductive wire is over the substrate. A second conductive wire is over the substrate and is adjacent to the first conductive wire. A first dielectric cap is laterally between the first conductive wire and the second conductive wire. The first dielectric cap laterally separates the first conductive wire from the second conductive wire. The first dielectric cap includes a first dielectric material. A first cavity is directly below the first dielectric cap and is laterally between the first conductive wire and the second conductive wire. The first cavity is defined by one or more surfaces of the first dielectric cap.

公开(公告)号：US20230282571A1

公开(公告)日：2023-09-07

申请号：US18313480

申请日：2023-05-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Pokuan Ho ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Wei-Chen Chu

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/528

Abstract: The present disclosure relates to an integrated chip that includes a substrate, a first metal line, and a hybrid metal line. The first metal line includes a first metal material and is within a first interlayer dielectric (ILD) layer over the substrate. The hybrid metal line is also within the first ILD layer. The hybrid metal line includes a pair of first metal segments that comprise the first metal material. The hybrid metal line further includes a second metal segment that comprises a second metal material that is different from the first metal material. The second metal segment is laterally between the pair of first metal segments.