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公开(公告)号：US12034076B2
公开(公告)日：2024-07-09
申请号：US17406884
申请日：2021-08-19
发明人： Chih-Liang Chen , Lei-Chun Chou , Jack Liu , Kam-Tou Sio , Hui-Ting Yang , Wei-Cheng Lin , Chun-Hung Liou , Jiann-Tyng Tzeng , Chew-Yuen Young
IPC分类号： H01L29/78 , H01L21/768 , H01L21/8234 , H01L23/48 , H01L23/528 , H01L23/535 , H01L27/088 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7851 , H01L21/76871 , H01L21/823431 , H01L21/823475 , H01L23/481 , H01L23/528 , H01L23/5286 , H01L23/535 , H01L27/0886 , H01L29/66795 , H01L29/41791
摘要： A semiconductor device includes a substrate, a dielectric region, a first fin structure, a second fin structure, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The first fin structure protrudes from the substrate and the dielectric region. The second fin structure protrudes from the substrate and the dielectric region, and extends parallel to the first fin structure. The conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and electrically connected to a first conductive region of the plurality of conductive regions. Opposite sides of the first conductive rail face the first fin structure and the second fin structure, respectively. The conductive structure penetrates through the substrate and formed under the first conductive rail, and is electrically connected to the first conductive rail.
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2.发明授权公开(公告)号：US11658182B2
公开(公告)日：2023-05-23
申请号：US17209730
申请日：2021-03-23
发明人： Kam-Tou Sio , Shang-Wei Fang , Jiann-Tyng Tzeng , Chew-Yuen Young
IPC分类号： H01L23/498 , H01L27/088 , H01L29/78 , H01L29/66 , H01L29/417 , H01L21/8238 , H01L27/092
CPC分类号： H01L27/0886 , H01L21/823821 , H01L23/49827 , H01L27/0924 , H01L29/41791 , H01L29/66795 , H01L29/785
摘要： An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, and a third portion of the first fin structure, the second fin structure and the third fin structure, respectively. Each of the first fin structure, the second fin structure and the third fin structure has a same type dopant. A first distance between the first fin structure and the second fin structure is different from a second distance between the second fin structure and the third fin structure.
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公开(公告)号：US10510776B2
公开(公告)日：2019-12-17
申请号：US15939876
申请日：2018-03-29
发明人： Jack Liu , Jiann-Tyng Tzeng , Chih-Liang Chen , Chew-Yuen Young , Sing-Kai Huang , Ching-Fang Huang
IPC分类号： H01L27/12 , H01L21/761 , H01L21/84 , H01L21/762 , H01L29/10
摘要： A semiconductor device includes a substrate, a pair of transistor devices and an isolation region. The pair of transistor devices are disposed over the substrate. Each of the pair of the transistor devices includes a channel, a gate electrode over the channel, and a source/drain region alongside the gate electrode. The isolation region is disposed between the source/drain regions of the pair of the transistor devices. The isolation region has a first doping type opposite to a second doping type of the source/drain regions.
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公开(公告)号：US11145678B2
公开(公告)日：2021-10-12
申请号：US16703483
申请日：2019-12-04
发明人： Jack Liu , Jiann-Tyng Tzeng , Chih-Liang Chen , Chew-Yuen Young , Sing-Kai Huang , Ching-Fang Huang
IPC分类号： H01L27/12 , H01L21/762 , H01L21/761 , H01L21/84 , H01L29/10
摘要： A method for manufacturing a semiconductor device includes following operations. A substrate including an active area is received. A plurality of source/drain regions of a plurality of transistor devices are formed in the active area. An isolation region is inserted between two adjacent source/drain regions of two adjacent transistor devices. The isolation region and the two adjacent source/drain regions cooperatively form two diode devices electrically connected in a back to back manner.
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公开(公告)号：US10700207B2
公开(公告)日：2020-06-30
申请号：US15993149
申请日：2018-05-30
发明人： Chih-Liang Chen , Lei-Chun Chou , Jack Liu , Kam-Tou Sio , Hui-Ting Yang , Wei-Cheng Lin , Chun-Hung Liou , Jiann-Tyng Tzeng , Chew-Yuen Young
IPC分类号： H01L29/78 , H01L29/66 , H01L23/528 , H01L27/088 , H01L23/535 , H01L21/768 , H01L21/8234 , H01L23/48 , H01L29/417
摘要： A semiconductor device includes a substrate, a dielectric region, a plurality of conductive regions, a first conductive rail and a conductive structure. The dielectric region is situated on the substrate. The plurality of conductive regions are situated on the dielectric region. The first conductive rail is situated within the dielectric region, and is electrically connected to a first conductive region of the plurality of conductive regions. The conductive structure is arranged to penetrate through the substrate and formed under the first conductive rail. The conductive structure is electrically connected to the first conductive rail.
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6.发明授权公开(公告)号：US12132049B2
公开(公告)日：2024-10-29
申请号：US18302769
申请日：2023-04-18
发明人： Kam-Tou Sio , Shang-Wei Fang , Jiann-Tyng Tzeng , Chew-Yuen Young
IPC分类号： H01L27/088 , H01L21/8238 , H01L23/498 , H01L27/092 , H01L29/417 , H01L29/66 , H01L29/78
CPC分类号： H01L27/0886 , H01L21/823821 , H01L23/49827 , H01L27/0924 , H01L29/41791 , H01L29/66795 , H01L29/785
摘要： An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, and a third portion of the first fin structure, the second fin structure and the third fin structure, respectively. Each of the first fin structure, the second fin structure and the third fin structure has a same type dopant. A first distance between the first fin structure and the second fin structure is different from a second distance between the second fin structure and the third fin structure.
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公开(公告)号：US11121256B2
公开(公告)日：2021-09-14
申请号：US16894228
申请日：2020-06-05
发明人： Chih-Liang Chen , Lei-Chun Chou , Jack Liu , Kam-Tou Sio , Hui-Ting Yang , Wei-Cheng Lin , Chun-Hung Liou , Jiann-Tyng Tzeng , Chew-Yuen Young
IPC分类号： H01L29/78 , H01L29/66 , H01L21/82 , H01L23/52 , H01L23/528 , H01L27/088 , H01L23/535 , H01L21/768 , H01L21/8234 , H01L23/48 , H01L29/417
摘要： A method for forming a non-planar semiconductor device includes: forming a fin structure protruding from a front side of a substrate of the non-planar semiconductor device; depositing a dielectric region on the front side of the substrate, the dielectric region including a conductive rail buried within the dielectric region and in parallel with the fin structure; etching the dielectric region to create a first opening in the dielectric region to expose the conductive rail; depositing a plurality of conductive regions on the dielectric region, one of the conductive regions contacting the conductive rail through the first opening; etching the substrate from a backside of the substrate to form a second opening to expose the conductive rail; and filling a first conductive material into the second opening to form a through-substrate via in the substrate.
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8.发明授权公开(公告)号：US10971493B2
公开(公告)日：2021-04-06
申请号：US16008111
申请日：2018-06-14
发明人： Kam-Tou Sio , Shang-Wei Fang , Jiann-Tyng Tzeng , Chew-Yuen Young
IPC分类号： H01L27/088 , H01L23/498 , H01L29/78 , H01L29/66 , H01L29/417 , H01L21/8238 , H01L27/092
摘要： An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; a fourth fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, a third portion, and a fourth portion of the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure respectively. A first distance between the first fin structure and the second fin structure is different from a second distance between the third fin structure and the fourth fin structure.
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公开(公告)号：US10169515B2
公开(公告)日：2019-01-01
申请号：US14942927
申请日：2015-11-16
发明人： Kam-Tou Sio , Tsung-Yao Wen , Chih-Ming Lai , Hui-Ting Yang , Jui-Yao Lai , Chih-Liang Chen , Chun-Kuang Chen , Ru-Gun Liu , Yen-Ming Chen , Chew-Yuen Young
IPC分类号： G06F17/50 , H01L21/027
摘要： A layout modification method is performed by at least one processor. The layout modification method includes: analyzing, by the at least one processor, allocation of a plurality of specific layout segments of a circuit cell layout to determine a first specific layout segment and a second specific layout segment from the plurality of specific layout segments; determining, by the at least one processor, if the first specific layout segment and the second specific layout segment are coupled to a first signal level; and merging, by the at least one processor, the first specific layout segment and the second specific layout segment into a first merged layout segment when the first specific layout segment and the second specific layout segment are coupled to the first signal level.
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公开(公告)号：US10162930B2
公开(公告)日：2018-12-25
申请号：US15229536
申请日：2016-08-05
发明人： Wei-Cheng Lin , Kam-Tou Sio , Shih-Wei Peng , Hui-Ting Yang′ , Chih-Liang Chen , Jiann-Tyng Tzeng , Chew-Yuen Young , Chia-Tien Wu , Chih-Ming Lai
IPC分类号： G06F17/50
摘要： A method performed by at least one processor comprises the operations of obtaining information on gate pitch and a ratio m:n between gate pitch and metal line pitch, m, n being a natural number and the ratio being in the simplest form, determining a unit pattern having a width of n times of the gate pitch, assigning m consecutive metal lines to the unit pattern, dividing the width of the unit pattern by m and obtaining a quotient (Q) and a remainder (R), determining an integer P so that a value of the remainder R divided by P satisfies a layout precision, and determining an inter-pattern metal line pitch and an intra-pattern metal line pitch based on Q and R/P.
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