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公开(公告)号：US20230317545A1
公开(公告)日：2023-10-05
申请号：US17710507
申请日：2022-03-31
申请人： Intel Corporation
发明人： Pilin Liu , Feras Eid , Michael Baker , Wenhao Li , Zhaozhi Li
IPC分类号： H01L23/367 , H01L23/00 , H01L23/373
CPC分类号： H01L23/367 , H01L24/16 , H01L24/17 , H01L24/08 , H01L24/09 , H01L24/81 , H01L23/3732 , H01L2924/37001 , H01L2924/3511 , H01L2224/81203 , H01L2224/10155 , H01L2224/16227 , H01L2224/16238 , H01L2224/16237 , H01L2224/16014 , H01L2224/16013 , H01L2224/16057 , H01L2224/1703 , H01L2224/17051 , H01L2224/17132 , H01L2224/17133 , H01L2224/0801 , H01L2224/0903 , H01L2224/09104 , H01L2224/08113
摘要： Microelectronic die package structures formed according to some embodiments may include a substrate and a die having a first side and a second side. The first side of the die is coupled to the substrate, and a die backside layer is on the second side of the die. The die backside layer includes a plurality of unfilled grooves in the die backside layer. Each of the unfilled grooves has an opening at a surface of the die backside layer, opposite the second side of the die, and extends at least partially through the die backside layer.
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2.发明申请公开(公告)号：US20130087910A1
公开(公告)日：2013-04-11
申请号：US13543907
申请日：2012-07-09
IPC分类号： H01L23/498
CPC分类号： H01L24/06 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05555 , H01L2224/05572 , H01L2224/0603 , H01L2224/0616 , H01L2224/09104 , H01L2224/131 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81191 , H01L2224/81815 , H01L2924/1461 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.
摘要翻译： 半导体管芯包括第一接触堆叠，第一接触堆叠包括在第一管芯焊盘上的第一UBM焊盘，在第二管芯焊盘上包括第二UBM焊盘的第二接触堆叠，以及在第三管芯焊盘上包括第三UBM焊盘的第三接触堆叠。 第二UBM垫周长比第一UBM垫周长短，而第三UBM垫周长比第二UBM垫周长长。 第一个焊料凸点位于第一个UBM焊盘上，第二个焊料凸块位于第二个UBM焊盘上，第三个焊料凸块位于第三个UBM焊盘上。 第一焊料凸块，第二焊料凸块和第三焊料凸块都具有不同的尺寸。
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公开(公告)号：US08860218B2
公开(公告)日：2014-10-14
申请号：US13269938
申请日：2011-10-10
CPC分类号： H01L24/06 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05555 , H01L2224/05572 , H01L2224/0603 , H01L2224/0616 , H01L2224/09104 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81191 , H01L2224/81815 , H01L2924/1461 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor die includes a first contact stack including a first die pad having a first pad perimeter, a first via through a dielectric layer to the first die pad having a first via perimeter, and a first UBM pad contacting the first die pad through the first via having a first UBM pad perimeter. A second contact stack includes a second die pad having a second pad perimeter shorter than the first pad perimeter, a second via through the dielectric layer to the second die pad having a second via perimeter shorter than the first via perimeter, and a second UBM pad contacting the second die pad through the second via having a second UBM pad perimeter that is shorter than the first UBM pad perimeter.
摘要翻译： 半导体管芯包括第一接触堆叠，第一接触堆叠包括具有第一焊盘周边的第一管芯焊盘，通过电介质层到第一管芯焊盘的第一通孔具有第一通孔周边，以及第一UBM焊盘，其通过第一焊盘接触第一裸片焊盘 通过具有第一UBM垫周长。 第二接触堆叠包括具有比第一焊盘周边短的第二焊盘周长的第二焊盘，通过电介质层到第二管芯焊盘的第二通孔具有比第一通孔周边短的第二通孔周边，以及第二UBM焊盘 使第二管芯焊盘穿过第二通孔，其具有比第一UBM焊盘周长短的第二UBM焊盘周边。
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4.发明授权Semiconductor device having multiple bump heights and multiple bump diameters 有权具有多个凸起高度和多个凸起直径的半导体器件公开(公告)号：US08704371B2
公开(公告)日：2014-04-22
申请号：US13543907
申请日：2012-07-09
IPC分类号： H01L23/498
CPC分类号： H01L24/06 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05555 , H01L2224/05572 , H01L2224/0603 , H01L2224/0616 , H01L2224/09104 , H01L2224/131 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81191 , H01L2224/81815 , H01L2924/1461 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/014 , H01L2924/00
摘要： A semiconductor die includes a first contact stack including a first UBM pad on a first die pad, a second contact stack including a second UBM pad on a second die pad, and a third contact stack including a third UBM pad on a third die pad. The second UBM pad perimeter is shorter than the first UBM pad perimeter, and the third UBM pad perimeter is longer than the second UBM pad perimeter. A first solder bump is on the first UBM pad, a second solder bump is on the second UBM pad, and a third solder bump is on the third UBM pad. The first solder bump, second solder bump and third solder bump all have different sizes.
摘要翻译： 半导体管芯包括第一接触堆叠，第一接触堆叠包括在第一管芯焊盘上的第一UBM焊盘，在第二管芯焊盘上包括第二UBM焊盘的第二接触堆叠，以及在第三管芯焊盘上包括第三UBM焊盘的第三接触堆叠。 第二UBM垫周长比第一UBM垫周长短，而第三UBM垫周长比第二UBM垫周长长。 第一个焊料凸点位于第一个UBM焊盘上，第二个焊料凸块位于第二个UBM焊盘上，第三个焊料凸块位于第三个UBM焊盘上。 第一焊料凸块，第二焊料凸块和第三焊料凸块都具有不同的尺寸。
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公开(公告)号：US20130087909A1
公开(公告)日：2013-04-11
申请号：US13269938
申请日：2011-10-10
IPC分类号： H01L23/498
CPC分类号： H01L24/06 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L2224/0401 , H01L2224/05022 , H01L2224/05555 , H01L2224/05572 , H01L2224/0603 , H01L2224/0616 , H01L2224/09104 , H01L2224/1403 , H01L2224/16225 , H01L2224/16227 , H01L2224/16238 , H01L2224/1703 , H01L2224/81191 , H01L2224/81815 , H01L2924/1461 , H01L2924/15311 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor die includes a first contact stack including a first die pad having a first pad perimeter, a first via through a dielectric layer to the first die pad having a first via perimeter, and a first UBM pad contacting the first die pad through the first via having a first UBM pad perimeter. A second contact stack includes a second die pad having a second pad perimeter shorter than the first pad perimeter, a second via through the dielectric layer to the second die pad having a second via perimeter shorter than the first via perimeter, and a second UBM pad contacting the second die pad through the second via having a second UBM pad perimeter that is shorter than the first UBM pad perimeter.
摘要翻译： 半导体管芯包括第一接触堆叠，第一接触堆叠包括具有第一焊盘周边的第一管芯焊盘，通过电介质层到第一管芯焊盘的第一通孔具有第一通孔周边，以及第一UBM焊盘，其通过第一焊盘接触第一裸片焊盘 通过具有第一UBM垫周长。 第二接触堆叠包括具有比第一焊盘周边短的第二焊盘周长的第二焊盘，通过电介质层到第二管芯焊盘的第二通孔具有比第一通孔周边短的第二通孔周边，以及第二UBM焊盘 使第二管芯焊盘穿过第二通孔，其具有比第一UBM焊盘周长短的第二UBM焊盘周边。
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公开(公告)号：US20130026630A1
公开(公告)日：2013-01-31
申请号：US13191632
申请日：2011-07-27
申请人： ChauChin Low
发明人： ChauChin Low
IPC分类号： H01L23/498 , H01L21/60
CPC分类号： H01L23/49811 , H01L23/49816 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0401 , H01L2224/06102 , H01L2224/09104 , H01L2224/1181 , H01L2224/131 , H01L2224/1403 , H01L2224/141 , H01L2224/1415 , H01L2224/16237 , H01L2224/16238 , H01L2224/81011 , H01L2224/81191 , H01L2224/81815 , H01L2924/00014 , H01L2924/014
摘要： In certain embodiments, a flip chip includes a first and second solder bump. The first solder bump has a solder bump height that is greater than the second solder bump.In certain embodiments, a method includes depositing solder on an integrated circuit, reflowing the solder to create at least two solder bumps between bond pads and the integrated circuit, wherein the at least two solder bumps have different solder bump heights. A bottom layer is sized to accommodate the different solder bump heights.
摘要翻译： 在某些实施例中，倒装芯片包括第一和第二焊料凸块。 第一焊料凸块的焊料凸起高度大于第二焊料凸块。 在某些实施例中，一种方法包括在集成电路上沉积焊料，回流焊料以在接合焊盘和集成电路之间产生至少两个焊料凸块，其中至少两个焊料凸块具有不同的焊料凸起高度。 底层的尺寸适应不同的焊料凸起高度。
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