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公开(公告)号：US09859204B2
公开(公告)日：2018-01-02
申请号：US15230889
申请日：2016-08-08
发明人： Myeong Soon Park , Hyunsoo Chung , Won-young Kim , Ae-nee Jang , Chanho Lee
CPC分类号： H01L23/50 , H01L24/02 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02371 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/0401 , H01L2224/05 , H01L2224/05553 , H01L2224/05555 , H01L2224/06131 , H01L2224/06135 , H01L2224/06139 , H01L2224/06151 , H01L2224/06152 , H01L2224/06155 , H01L2224/06156 , H01L2224/06159 , H01L2224/0616 , H01L2224/06165 , H01L2224/06169 , H01L2224/06177 , H01L2224/06181 , H01L2224/13022 , H01L2224/131 , H01L2224/1403 , H01L2224/14181 , H01L2224/16227 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/0613
摘要： Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.
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公开(公告)号：US09159705B2
公开(公告)日：2015-10-13
申请号：US14303987
申请日：2014-06-13
发明人： Chul-yong Jang , Ae-nee Jang , Young-lyong Kim
IPC分类号： H01L23/02 , H01L23/52 , H01L25/11 , H01L27/146 , H01L25/065 , H01L23/00 , H01L25/00 , H01L23/31 , H01L23/525
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2224/02371 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/92244 , H01L2224/94 , H01L2225/06524 , H01L2225/06562 , H01L2225/06565 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2224/03 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one semiconductor chip in a first direction in which the chip connection pad faces toward an edge of the at least one semiconductor chip. At least one interconnection line disposed on a side of the at least one semiconductor chip electrically connects the substrate connection pad to the at least one redistribution layer. The at least one redistribution layer includes a protruding portion protruding from the edge of the at least one semiconductor chip to contact the at least one interconnection line.
摘要翻译： 半导体封装包括包括衬底连接焊盘的封装衬底。 至少一个半导体芯片包括至少一个再分配层。 所述至少一个再分配层覆盖芯片连接焊盘的至少一部分，并且沿着第一方向沿着至少一个半导体芯片的上表面延伸，其中芯片连接焊盘朝向至少一个半导体芯片的边缘 。 设置在所述至少一个半导体芯片的一侧上的至少一个互连线将所述衬底连接焊盘电连接到所述至少一个再分配层。 所述至少一个再分布层包括从所述至少一个半导体芯片的边缘突出以与所述至少一个互连线接触的突出部分。
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3.发明授权公开(公告)号：US09570423B2
公开(公告)日：2017-02-14
申请号：US14957561
申请日：2015-12-02
发明人： Chul-yong Jang , Young-lyong Kim , Ae-nee Jang
IPC分类号： H01L23/48 , H01L25/065 , H01L23/31 , H01L23/498 , H01L23/538 , H01L21/56 , H01L23/00 , H01L25/00 , H01L21/48
CPC分类号： H01L25/0657 , H01L21/4853 , H01L21/486 , H01L21/568 , H01L23/3128 , H01L23/481 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/13 , H01L24/16 , H01L24/19 , H01L24/27 , H01L24/32 , H01L24/73 , H01L24/82 , H01L24/96 , H01L25/50 , H01L2224/11849 , H01L2224/12105 , H01L2224/13023 , H01L2224/13082 , H01L2224/13111 , H01L2224/13116 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/14155 , H01L2224/16058 , H01L2224/16235 , H01L2224/16237 , H01L2224/2746 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/33181 , H01L2224/48228 , H01L2224/73265 , H01L2224/73267 , H01L2224/81191 , H01L2224/81193 , H01L2224/81203 , H01L2224/81447 , H01L2224/81815 , H01L2224/8203 , H01L2224/92244 , H01L2224/96 , H01L2224/97 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06562 , H01L2225/06586 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2924/18161 , H01L2924/18162 , H01L2924/00014 , H01L2924/014 , H01L2224/83 , H01L2224/11 , H01L2924/00 , H01L2924/00012
摘要： Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.
摘要翻译： 本发明构思的实施例包括具有多个堆叠的半导体芯片的半导体封装。 多层基板包括中心绝缘层，设置在中心绝缘层的上表面上的上布线层和设置在中心绝缘层的下表面上的第一下布线层。 堆叠的半导体芯片使用各种手段连接到多层基板和/或彼此。 该半导体封装能够进行高性能的操作，例如基于翻转式接合的半导体封装，并且通过克服由单个半导体芯片引起的限制来满足大容量的需要。 本发明构思的实施例还包括制造半导体封装的方法。
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公开(公告)号：US20170084559A1
公开(公告)日：2017-03-23
申请号：US15230889
申请日：2016-08-08
发明人： Myeong Soon Park , Hyunsoo Chung , Won-young Kim , Ae-nee Jang , Chanho Lee
IPC分类号： H01L23/00
CPC分类号： H01L23/50 , H01L24/02 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02371 , H01L2224/02372 , H01L2224/02375 , H01L2224/02377 , H01L2224/02379 , H01L2224/0401 , H01L2224/05 , H01L2224/05553 , H01L2224/05555 , H01L2224/06131 , H01L2224/06135 , H01L2224/06139 , H01L2224/06151 , H01L2224/06152 , H01L2224/06155 , H01L2224/06156 , H01L2224/06159 , H01L2224/0616 , H01L2224/06165 , H01L2224/06169 , H01L2224/06177 , H01L2224/06181 , H01L2224/13022 , H01L2224/131 , H01L2224/1403 , H01L2224/14181 , H01L2224/16227 , H01L2924/014 , H01L2924/00014 , H01L2924/00012 , H01L2224/0613
摘要： Semiconductor devices with redistribution pads are disclosed. The semiconductor device includes a plurality of electric pads provided on a semiconductor substrate, and a plurality of redistribution pads electrically connected to the electric pads and an outer terminal. The plurality of redistribution pads includes a plurality of first redistribution pads constituting a transmission path for a first electrical signal and at least one second redistribution pad constituting a transmission path for a second electrical signal different from the first electrical signal. The first redistribution pads are arranged on the semiconductor substrate to form at least two rows, and the at least one second redistribution pad is disposed between the at least two rows of the first redistribution pads.
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公开(公告)号：US10943881B2
公开(公告)日：2021-03-09
申请号：US16244661
申请日：2019-01-10
发明人： Ae-nee Jang , KyungSeon Hwang , SunWon Kang
IPC分类号： H01L23/488 , H01L23/00 , H01L21/56 , H01L23/48
摘要： A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
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公开(公告)号：US10211176B2
公开(公告)日：2019-02-19
申请号：US15375196
申请日：2016-12-12
发明人： Ae-nee Jang , KyungSeon Hwang , SunWon Kang
IPC分类号： H01L27/146 , H01L23/00 , H01L21/56 , H01L23/48
摘要： A semiconductor package includes a substrate, through-electrodes penetrating the substrate, first bumps spaced apart from each other in a first direction parallel to a top surface of the substrate and electrically connected to the through-electrodes, respectively, and at least one second bump disposed between the first bumps and electrically insulated from the through-electrodes. The first bumps and the at least one second bump constitute one row in the first direction. A level of a bottom surface of the at least one second bump from the top surface of the substrate is a substantially same as levels of bottom surfaces of the first bumps from the top surface of the substrate.
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公开(公告)号：US20150014860A1
公开(公告)日：2015-01-15
申请号：US14303987
申请日：2014-06-13
发明人： Chul-yong Jang , Ae-nee Jang , Young-Iyong Kim
IPC分类号： H01L23/538 , H01L25/065
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/24 , H01L24/82 , H01L25/50 , H01L2224/02371 , H01L2224/24145 , H01L2224/24226 , H01L2224/32145 , H01L2224/32225 , H01L2224/92244 , H01L2224/94 , H01L2225/06524 , H01L2225/06562 , H01L2225/06565 , H01L2924/12042 , H01L2924/15311 , H01L2924/181 , H01L2224/03 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one semiconductor chip in a first direction in which the chip connection pad faces toward an edge of the at least one semiconductor chip. At least one interconnection line disposed on a side of the at least one semiconductor chip electrically connects the substrate connection pad to the at least one redistribution layer. The at least one redistribution layer includes a protruding portion protruding from the edge of the at least one semiconductor chip to contact the at least one interconnection line.
摘要翻译： 半导体封装包括包括衬底连接焊盘的封装衬底。 至少一个半导体芯片包括至少一个再分配层。 所述至少一个再分配层覆盖芯片连接焊盘的至少一部分，并且沿着第一方向沿着至少一个半导体芯片的上表面延伸，其中芯片连接焊盘朝向至少一个半导体芯片的边缘 。 设置在所述至少一个半导体芯片的一侧上的至少一个互连线将所述衬底连接焊盘电连接到所述至少一个再分配层。 所述至少一个再分布层包括从所述至少一个半导体芯片的边缘突出以与所述至少一个互连线接触的突出部分。
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