公开(公告)号：US09159705B2

公开(公告)日：2015-10-13

申请号：US14303987

申请日：2014-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-yong Jang ,  Ae-nee Jang ,  Young-lyong Kim

IPC: H01L23/02 ,  H01L23/52 ,  H01L25/11 ,  H01L27/146 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L23/525

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2224/02371 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one semiconductor chip in a first direction in which the chip connection pad faces toward an edge of the at least one semiconductor chip. At least one interconnection line disposed on a side of the at least one semiconductor chip electrically connects the substrate connection pad to the at least one redistribution layer. The at least one redistribution layer includes a protruding portion protruding from the edge of the at least one semiconductor chip to contact the at least one interconnection line.

Abstract translation: 半导体封装包括包括衬底连接焊盘的封装衬底。 至少一个半导体芯片包括至少一个再分配层。 所述至少一个再分配层覆盖芯片连接焊盘的至少一部分，并且沿着第一方向沿着至少一个半导体芯片的上表面延伸，其中芯片连接焊盘朝向至少一个半导体芯片的边缘 。 设置在所述至少一个半导体芯片的一侧上的至少一个互连线将所述衬底连接焊盘电连接到所述至少一个再分配层。 所述至少一个再分布层包括从所述至少一个半导体芯片的边缘突出以与所述至少一个互连线接触的突出部分。

公开(公告)号：US09570423B2

公开(公告)日：2017-02-14

申请号：US14957561

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-yong Jang ,  Young-lyong Kim ,  Ae-nee Jang

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00 ,  H01L21/48

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/27 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/14155 ,  H01L2224/16058 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/2746 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48228 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81203 ,  H01L2224/81447 ,  H01L2224/81815 ,  H01L2224/8203 ,  H01L2224/92244 ,  H01L2224/96 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06586 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

Abstract translation: 本发明构思的实施例包括具有多个堆叠的半导体芯片的半导体封装。 多层基板包括中心绝缘层，设置在中心绝缘层的上表面上的上布线层和设置在中心绝缘层的下表面上的第一下布线层。 堆叠的半导体芯片使用各种手段连接到多层基板和/或彼此。 该半导体封装能够进行高性能的操作，例如基于翻转式接合的半导体封装，并且通过克服由单个半导体芯片引起的限制来满足大容量的需要。 本发明构思的实施例还包括制造半导体封装的方法。

公开(公告)号：US09281235B2

公开(公告)日：2016-03-08

申请号：US14613154

申请日：2015-02-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-lyong Kim ,  Taehoon Kim ,  Jongho Lee ,  Chul-Yong Jang

IPC: H01L21/768 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L21/76802 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3185 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/24146 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/92144 ,  H01L2225/06524 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01012 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

公开(公告)号：US10438899B2

公开(公告)日：2019-10-08

申请号：US15869517

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-lyong Kim ,  Hyun-soo Chung ,  Dong-hyeon Jang

IPC: H01L23/552 ,  H01L23/538 ,  H01L23/00 ,  H01L23/34 ,  H01L23/367 ,  H01L23/433 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

公开(公告)号：US08884446B2

公开(公告)日：2014-11-11

申请号：US13792942

申请日：2013-03-11

Applicant: Samsung Electronics Co., Ltd

Inventor： Young-lyong Kim ,  Seong-ho Shin ,  Jae-gwon Jang ,  Jong-ho Lee

IPC: H01L23/48 ,  H01L23/00

CPC classification number: H01L24/46 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2924/10161 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/45664 ,  H01L2924/00012

Abstract: A semiconductor package includes a master chip and a slave chip stacked on a substrate. The master chip and the slave chip are connected to one another by a bonding wire. The master chip and the slave chip are connected in series with an external circuit. The semiconductor package may have a low loading factor and excellent performance, and may be mass produced at low costs.

Abstract translation: 半导体封装包括堆叠在基板上的主芯片和从芯片。 主芯片和从芯片通过接合线彼此连接。 主芯片和从芯片与外部电路串联连接。 半导体封装可以具有低负载率和优异的性能，并且可以以低成本批量生产。

公开(公告)号：US11031347B2

公开(公告)日：2021-06-08

申请号：US16381319

申请日：2019-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-lyong Kim ,  Hyun-soo Chung ,  Dong-hyeon Jang

IPC: H01L23/552 ,  H01L23/538 ,  H01L23/00 ,  H01L23/34 ,  H01L23/367 ,  H01L23/433 ,  H01L25/065 ,  H01L25/10 ,  H01L23/498

Abstract: A semiconductor package including a heat spreading layer having at least one hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole may be provided.

公开(公告)号：US20130161784A1

公开(公告)日：2013-06-27

申请号：US13651465

申请日：2012-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chul-yong Jang ,  Young-lyong Kim

IPC: H01L29/02

CPC classification number: H01L23/49838 ,  H01L23/3128 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package includes a substrate; first and second pads that are disposed separate from each other on the substrate; and a solder resist that allows a portion of the substrate in a region between the first and second pads and to be exposed while covering a portion of the first and second pads in a region other than the region between the first and second pads.

Abstract translation: 半导体封装包括基板; 在基板上彼此分离设置的第一和第二焊盘; 以及阻焊剂，其允许基板的一部分在第一和第二焊盘之间的区域中并且在第一和第二焊盘之间的区域之外的区域中覆盖第一焊盘和第二焊盘的一部分时被暴露。