公开(公告)号：US11990464B2

公开(公告)日：2024-05-21

申请号：US17204797

申请日：2021-03-17

Applicant: SOCIONEXT INC.

Inventor： Toru Matsui

IPC: H01L27/02 ,  H01L27/11 ,  H01L27/118

CPC classification number: H01L27/0207 ,  H01L27/11898 ,  H01L2224/0613 ,  H01L2224/06134 ,  H01L2224/0616 ,  H01L2224/06163 ,  H01L2224/06177

Abstract: Provided is a semiconductor integrated circuit device including a plurality of columns of IO cells and having a configuration capable of reducing wiring delays without causing an increase in the area. The semiconductor integrated circuit device includes a first IO cell column group including an IO cell column closest to a periphery of a chip, and a second IO cell column group including an IO cell column adjacent to the first IO cell column group at the side closer to the core region. At least one of the first IO cell column group or the second IO cell column group includes two or more IO cell columns, and the two or more IO cell columns are aligned in the second direction such that the lower power supply voltage regions face each other or the higher power supply voltage regions face each other.