公开(公告)号：US20240186248A1

公开(公告)日：2024-06-06

申请号：US18523131

申请日：2023-11-29

申请人： ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

发明人： Belgacem HABA ,  Cyprian Emeka UZOH ,  Rajesh KATKAR

IPC分类号： H01L23/528 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L25/065

CPC分类号： H01L23/5286 ,  H01L23/3672 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0657 ,  H01L2224/05009 ,  H01L2224/05025 ,  H01L2224/13007 ,  H01L2224/13026 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2924/01029 ,  H01L2924/1427 ,  H01L2924/1431 ,  H01L2924/15311

摘要： An assembly may include a reconstituted element having a front surface and a back surface, the reconstituted element comprising: a semiconductor die having a front side and a back side, the semiconductor die including circuitry closer to the front side than to the back side and a via extending from the back side of the semiconductor die to connect to the circuitry, an insulating material disposed along a side surface of the semiconductor die, a power rail extending from the front surface to the back surface of the reconstituted element and configured to deliver power to the semiconductor die; and an interconnect structure configured to electrically connect the power rail to the via and to deliver power to the semiconductor die from the back side of the semiconductor die.

公开(公告)号：US20230187398A1

公开(公告)日：2023-06-15

申请号：US18147375

申请日：2022-12-28

申请人： Adeia Semiconductor Bonding Technologies Inc.

发明人： Guilian GAO ,  Javier A. DELACRUZ ,  Shaowu HUANG ,  Liang WANG ,  Gaius Giliman FOUNTAIN, JR. ,  Rajesh KATKAR ,  Cyprian Emeka UZOH

IPC分类号： H01L23/00

CPC分类号： H01L24/08 ,  H01L24/05 ,  H01L24/06 ,  H01L24/74 ,  H01L24/80 ,  H01L24/89 ,  H01L2224/05557 ,  H01L2224/06131 ,  H01L2224/06177 ,  H01L2224/8013 ,  H01L2224/08147 ,  H01L2224/80007 ,  H01L2224/80011 ,  H01L2224/80031 ,  H01L2224/80047 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/3512

摘要： Structures and techniques provide bond enhancement in microelectronics by trapping contaminants and byproducts during bonding processes, and arresting cracks. Example bonding surfaces are provided with recesses, sinks, traps, or cavities to capture small particles and gaseous byproducts of bonding that would otherwise create detrimental voids between microscale surfaces being joined, and to arrest cracks. Such random voids would compromise bond integrity and electrical conductivity of interconnects being bonded. In example systems, a predesigned recess space or predesigned pattern of recesses placed in the bonding interface captures particles and gases, reducing the formation of random voids, thereby improving and protecting the bond as it forms. The recess space or pattern of recesses may be placed where particles collect on the bonding surface, through example methods of determining where mobilized particles move during bond wave propagation. A recess may be repeated in a stepped reticule pattern at the wafer level, for example, or placed by an aligner or alignment process.

公开(公告)号：US20240332267A1

公开(公告)日：2024-10-03

申请号：US18617086

申请日：2024-03-26

申请人： Adeia Semiconductor Bonding Technologies, Inc.

发明人： Belgacem HABA ,  Cyprian Emeka UZOH ,  Rajesh KATKAR

IPC分类号： H01L25/10 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L23/528

CPC分类号： H01L25/105 ,  H01L21/4857 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/5286 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2224/08225

摘要： In some embodiments, a structure comprises an active element having a frontside and a backside opposite the frontside, the active element having active circuitry nearer the frontside than the backside and a power redistribution element having a frontside hybrid bonded to the backside of the active element, the power redistribution element comprising a first plurality of contact pads on the frontside of the power redistribution element and a second plurality of contact pads on a backside of the power redistribution element opposite the frontside of the power redistribution element, a pitch of the first plurality of contact pads is smaller than a pitch of the second plurality of contact pads, the power redistribution element configured to supply at least one of power and ground to the active element.

公开(公告)号：US20230343734A1

公开(公告)日：2023-10-26

申请号：US18305149

申请日：2023-04-21

申请人： ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

发明人： Cyprian Emeka UZOH ,  Oliver ZHAO ,  Bongsub LEE ,  Laura Wills MIRKARIMI ,  Dominik SUWITO

IPC分类号： H01L23/00

CPC分类号： H01L24/05 ,  H01L24/03 ,  H01L24/08 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05611 ,  H01L2224/05609 ,  H01L2224/05663 ,  H01L2924/01005 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05684 ,  H01L2224/0567 ,  H01L2224/0568 ,  H01L2924/0132 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05111 ,  H01L2224/05026 ,  H01L2224/05073 ,  H01L2224/05109 ,  H01L2224/05147 ,  H01L2224/05157 ,  H01L2224/05155 ,  H01L2224/0517 ,  H01L2224/05172 ,  H01L2224/0518 ,  H01L2224/05184 ,  H01L2224/05163 ,  H01L2224/03614 ,  H01L2224/03464 ,  H01L2224/03452 ,  H01L2224/03845 ,  H01L2224/08059 ,  H01L2224/08145 ,  H01L24/80 ,  H01L2224/80895

摘要： An element, a bonded structure including the element, and a method forming the element and the bonded structure are disclosed. The element can include a non-conductive region having a cavity. The element can include a conductive feature formed in the cavity. The conductive feature includes a center portion and an edge portion having first and second coefficients of thermal expansion respectively. The center and edge portions are recessed relative to a contact surface of the non-conductive region by a first depth and a second depth respectively. The first coefficient of thermal expansion can be at least 5% greater than the second coefficient of thermal expansion. The bonded structure can include the element and a second element having a second non-conductive region and a second conductive feature. A conductive interface between the first and second conductive features has a center region and an edge region. In a side cross-section of the bonded structure, there are more voids at or near the edge region than at or near the center region.

公开(公告)号：US20240071915A1

公开(公告)日：2024-02-29

申请号：US18342515

申请日：2023-06-27

申请人： ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.

发明人： Cyprian Emeka UZOH

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L23/528 ,  H01L21/76898

摘要： Techniques are employed to mitigate the anchoring effects of cavity sidewall adhesion on an embedded conductive interconnect structure, and to allow a lower annealing temperature to be used to join opposing conductive interconnect structures. A vertical gap may be disposed between the conductive material of an embedded interconnect structure and the sidewall of the cavity to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material. Additionally or alternatively, one or more vertical gaps may be disposed within the bonding layer, near the embedded interconnect structure to laterally unpin the conductive structure and allow uniaxial expansion of the conductive material.