公开(公告)号：US10068836B2

公开(公告)日：2018-09-04

申请号：US15481802

申请日：2017-04-07

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chien-Chih Ho ,  Chih-Ping Chao ,  Hua-Chou Tseng ,  Chun-Hung Chen ,  Chia-Yi Su ,  Alex Kalnitsky ,  Jye-Yen Cheng ,  Harry-Hak-Lay Chuang

IPC分类号： H01L21/8238 ,  H01L23/48 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/768

摘要： An integrated circuit includes a substrate, a first inter-layer dielectric (ILD) layer over the substrate, and a gate strip having a first width formed in the first ILD layer. A conductive strip having a second width is provided on the gate strip, with the second width being greater than the first width. The conductive strip is positioned so that the gate strip is covered and a portion of the conductive strip extends over a top surface of the first ILD adjacent the gate strip. A second ILD layer is provided over the conductive strip and the first ILD layer with a contact plug extending through the second ILD layer to provide electrical contact to the conductive strip.

公开(公告)号：US09583564B2

公开(公告)日：2017-02-28

申请号：US14177451

申请日：2014-02-11

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Jenn Yu ,  Meng-Wei Hsieh ,  Shih-Hsien Yang ,  Hua-Chou Tseng ,  Chih-Ping Chao

IPC分类号： H01L29/78 ,  H01L21/761 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L29/0646 ,  H01L21/761 ,  H01L21/7624 ,  H01L29/0619 ,  H01L29/1087 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A structure comprises a p-type substrate, a deep n-type well and a deep p-type well. The deep n-type well is adjacent to the p-type substrate and has a first conductive path to a first terminal. The deep p-type well is in the deep n-type well, is separated from the p-type substrate by the deep n-type well, and has a second conductive path to a second terminal. A first n-type well is over the deep p-type well. A first p-type well is over the deep p-type well.

摘要翻译： 结构包括p型衬底，深n型阱和深p型阱。 深n型阱与p型衬底相邻并且具有到第一端子的第一导电路径。 深p型阱在深n型阱中，通过深n型阱与p型衬底分离，并具有到第二端的第二导电路径。 第一个n型井在深P型井上。 第一个p型井在深p型井上。

公开(公告)号：US20240355728A1

公开(公告)日：2024-10-24

申请号：US18451263

申请日：2023-08-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Kai-Chun Chang ,  Hsieh-Hung Hsieh ,  Tzu-Jin Yeh ,  Ching-Chung Hsu ,  Chung-Long Chang ,  Hua-Chou Tseng

IPC分类号： H01L23/522 ,  H01L23/00 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/5227 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/53219 ,  H01L23/53233 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02313 ,  H01L2224/02331 ,  H01L2224/0235 ,  H01L2224/02373 ,  H01L2224/02375 ,  H01L2224/02381 ,  H01L2224/0239 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/13007 ,  H01L2924/30107

摘要： A semiconductor structure includes a circuit with a redistribution layer (RDL) formed over the circuit. The redistribution layer comprises a plurality of metal layers. An inductor is formed in a topmost metal layer, and the circuit is located directly under the inductor. An under bump metallization (UBM) layer formed on the topmost metal layer and a conductive connector formed on the UBM layer.

公开(公告)号：US09431251B2

公开(公告)日：2016-08-30

申请号：US14626259

申请日：2015-02-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Hua-Chou Tseng ,  Chien-Chih Ho

IPC分类号： H01L29/78 ,  H01L21/266 ,  H01L29/10 ,  H01L21/761 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L21/266 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/1079 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

摘要： A method of forming a semiconductor device includes patterning a first mask over a substrate defining a first opening. The substrate includes a first dopant type. The method includes implanting ions having a second dopant type through the first opening to form a first deep well. The method includes patterning a second mask over the substrate defining a second opening. The method includes implanting ions having the second dopant type through the second opening to form a second deep well, wherein an energy for implanting ions to form the second deep well is lower than an energy for implanting ions to form the first deep well. The method includes implanting ions having the first dopant type into the substrate to form a first well, wherein the energy for implanting ions to form the second deep well is greater than an energy for implanting ions to form the first well.

摘要翻译： 形成半导体器件的方法包括在限定第一开口的衬底上图案化第一掩模。 衬底包括第一掺杂剂类型。 该方法包括通过第一开口注入具有第二掺杂剂类型的离子以形成第一深阱。 该方法包括在限定第二开口的衬底上图案化第二掩模。 该方法包括通过第二开口注入具有第二掺杂剂类型的离子以形成第二深阱，其中用于注入离子以形成第二深阱的能量低于用于注入离子以形成第一深阱的能量。 该方法包括将具有第一掺杂剂类型的离子注入到衬底中以形成第一阱，其中用于注入离子以形成第二深阱的能量大于用于注入离子以形成第一阱的能量。

公开(公告)号：US08987825B2

公开(公告)日：2015-03-24

申请号：US13913921

申请日：2013-06-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hua-Chou Tseng ,  Chien-Chih Ho

IPC分类号： H01L23/62 ,  H01L29/10

CPC分类号： H01L21/266 ,  H01L21/26513 ,  H01L21/761 ,  H01L29/1079 ,  H01L29/66568 ,  H01L29/66575 ,  H01L29/78

摘要： A semiconductor device includes a substrate having a first type doping. The semiconductor device further includes a first deep well in the substrate, the first deep well having a second type doping. The semiconductor device further includes a second deep well in the substrate, the second deep well having the second type doping and being separated and above the first deep well. The semiconductor device further includes a first well over the second deep well, the first well having the first type doping and a gate structure over the first well.

摘要翻译： 半导体器件包括具有第一类掺杂的衬底。 半导体器件还包括衬底中的第一深阱，第一深阱具有第二类掺杂。 所述半导体器件还包括在所述衬底中的第二深阱，所述第二深阱具有所述第二类型掺杂并且分离并位于所述第一深阱之上。 所述半导体器件还包括位于所述第二深阱上的第一阱，所述第一阱具有所述第一类型掺杂和所述第一阱上的栅极结构。

公开(公告)号：US10102972B2

公开(公告)日：2018-10-16

申请号：US14612740

申请日：2015-02-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Wei-Chun Hua ,  Chung-Long Chang ,  Chun-Hung Chen ,  Chih-Ping Chao ,  Jye-Yen Cheng ,  Hua-Chou Tseng

IPC分类号： H01G4/005 ,  H01L23/522 ,  H01L49/02

摘要： A method of forming a capacitor structure includes forming a first set of electrodes having a first electrode and a second electrode, wherein each electrode of the first set of electrodes has an L-shaped portion. The method further includes forming a second set of electrodes having a third electrode and a fourth electrode, wherein each electrode of the second set of electrodes has an L-shaped portion. The method further includes forming insulation layers between the first set of electrodes and the second set of electrodes. The method further includes forming a first L-shaped line plug connecting the first electrode to the third electrode, wherein an entirety of an outer surface of the first L-shaped line plug is recessed with respect to an outer surface of the L-shaped portion of the first electrode. The method further includes forming a second line plug connecting the second electrode to the fourth electrode.