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公开(公告)号：US20240379656A1
公开(公告)日：2024-11-14
申请号：US18780581
申请日：2024-07-23
Inventor： Yi Ching Ong , Kuen-Yi Chen , Yi-Hsuan Chen , Kuo-Ching Huang , Harry-Hak-Lay Chuang
IPC: H01L27/06 , H01L23/495 , H01L23/538
Abstract: The present disclosure relates to an integrated chip including a first metal layer over a substrate. A second metal layer is over the first metal layer. An ionic crystal layer is between the first metal layer and the second metal layer. A metal oxide layer is between the first metal layer and the second metal layer. The first metal layer, the second metal layer, the ionic crystal layer, and the metal oxide layer are over a transistor device that is arranged along the substrate.
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公开(公告)号：US20240379486A1
公开(公告)日：2024-11-14
申请号：US18777739
申请日：2024-07-19
Inventor： Harry-Hak-Lay Chuang , Hsin Fu Lin , Shiang-Hung Huang , Tsung-Hao Yeh
IPC: H01L23/367 , H01L21/762 , H01L21/84 , H01L23/528 , H01L27/12
Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a substrate. A semiconductor device is disposed on the substrate. An interlayer dielectric (ILD) structure is disposed over the substrate and the semiconductor device. A first intermetal dielectric (IMD) structure is disposed over the substrate and the ILD structure. An opening is disposed in the first IMD structure. The opening overlies at least a portion of the semiconductor device.
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公开(公告)号：US12133470B2
公开(公告)日：2024-10-29
申请号：US18059073
申请日：2022-11-28
Inventor： Harry-Hak-Lay Chuang , Kuei-Hung Shen , Chern-Yow Hsu , Shih-Chang Liu
Abstract: The present disclosure provides a semiconductor structure, including an Nth metal layer over a transistor region, where N is a natural number, and a bottom electrode over the Nth metal layer. The bottom electrode comprises a bottom portion having a first width, disposed in a bottom electrode via (BEVA), the first width being measured at a top surface of the BEVA, and an upper portion having a second width, disposed over the bottom portion. The semiconductor structure also includes a magnetic tunneling junction (MTJ) layer having a third width, disposed over the upper portion, a top electrode over the MTJ layer and an (N+1)th metal layer over the top electrode. The first width is greater than the third width.
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4.发明公开公开(公告)号：US20240178303A1
公开(公告)日：2024-05-30
申请号：US18432985
申请日：2024-02-05
Inventor： Harry-Hak-Lay Chuang , Yi-Ren Chen , Chi-Wen Liu , Chao-Hsiung Wang , Ming Zhu
IPC: H01L29/66 , H01L21/8234 , H01L21/8238 , H01L27/08 , H01L27/092 , H01L29/78
CPC classification number: H01L29/66977 , H01L21/823487 , H01L21/823885 , H01L27/0802 , H01L27/092 , H01L28/20 , H01L29/66666 , H01L29/785
Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
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5.发明授权公开(公告)号：US11894448B2
公开(公告)日：2024-02-06
申请号：US17406861
申请日：2021-08-19
Inventor： Harry-Hak-Lay Chuang , Yi-Ren Chen , Chi-Wen Liu , Chao-Hsiung Wang , Ming Zhu
IPC: H01L29/66 , H01L27/08 , H01L21/8234 , H01L27/092 , H01L21/8238 , H01L29/78 , H01L49/02
CPC classification number: H01L29/66977 , H01L21/823487 , H01L21/823885 , H01L27/0802 , H01L27/092 , H01L28/20 , H01L29/66666 , H01L29/785
Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
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Patent Agency Ranking
公开(公告)号：US11889769B2
公开(公告)日：2024-01-30
申请号：US17872520
申请日：2022-07-25
Inventor： Ming-Che Ku , Harry-Hak-Lay Chuang , Hung Cho Wang , Tsun Chung Tu , Jiunyu Tsai , Sheng-Huang Huang
IPC: H10N50/80 , H01F10/32 , H01F41/34 , H01L21/768 , H01L23/522 , H01L23/528 , H10B61/00 , H10N50/01 , G11C11/16
CPC classification number: H10N50/80 , H01F10/3254 , H01F41/34 , H01L21/76802 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H10B61/22 , H10N50/01 , G11C11/161
Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate. The top electrode has a width that decreases as a height of the top electrode increases. A bottom electrode via couples the bottom electrode to a lower interconnect. An upper interconnect structure is coupled to the top electrode. The upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode. The vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.
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公开(公告)号：US20230389445A1
公开(公告)日：2023-11-30
申请号：US18364697
申请日：2023-08-03
Inventor： Yao-Wen Chang , Chung-Chiang Min , Harry-Hak-Lay Chuang , Hung Cho Wang , Tsung-Hsueh Yang , Yuan-Tai Tseng , Sheng-Huang Huang , Chia-Hua Lin
Abstract: Various embodiments of the present disclosure are directed towards a method for forming an integrated chip. The method includes forming a memory cell stack over a substrate. The memory cell stack includes a top electrode. A sidewall spacer structure is formed around the memory cell stack. The sidewall spacer structure includes a first sidewall spacer layer, a second sidewall spacer layer, and a protective sidewall spacer layer sandwiched between the first and second sidewall spacer layers. A dielectric structure is formed over the sidewall spacer structure. A first etch process is performed on the dielectric structure and the second sidewall spacer layer to define an opening above the top electrode. The second sidewall spacer layer and the dielectric structure are etched at a higher rate than the protective sidewall spacer layer during the first etch process. A top electrode via is formed within the opening.
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公开(公告)号：US20230389324A1
公开(公告)日：2023-11-30
申请号：US18181229
申请日：2023-03-09
Inventor： Yi-Hsuan Chen , Kuen-Yi Chen , Yi Ching Ong , Yu-Wei Ting , Kuo-Chi Tu , Kuo-Ching Huang , Harry-Hak-Lay Chuang
IPC: H10B51/20 , H01L21/28 , H01L29/51 , H01L29/66 , H01L29/78 , H01L23/522 , H01L23/528
CPC classification number: H10B51/20 , H01L29/40111 , H01L29/516 , H01L29/6684 , H01L29/78391 , H01L23/5226 , H01L23/5283
Abstract: A method of forming a memory device according to the present disclosure includes forming a trench in a first substrate of a first wafer, depositing a data-storage element in the trench, performing a thermal treatment to the first wafer to improve a crystallization in the data-storage element, forming a first redistribution layer over the first substrate, forming a transistor in a second substrate of a second wafer, forming a second redistribution layer over the second substrate, and bonding the first wafer with the second wafer after the performing of the thermal treatment. The data-storage element is electrically coupled to the transistor through the first and second redistribution layers.
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9.发明公开公开(公告)号：US20230317629A1
公开(公告)日：2023-10-05
申请号：US18332047
申请日：2023-06-09
Inventor： Harry-Hak-Lay Chuang , Tien-Wei Chiang , Kuo-An Liu , Chia-Hsiang Chen
IPC: H01L23/552 , H01L23/495 , H01L23/00 , H10B61/00 , H10N50/01 , H10N50/80
CPC classification number: H01L23/552 , H01L23/49555 , H01L24/48 , H01L24/49 , H10B61/00 , H10N50/01 , H10N50/80 , H01L2924/3025 , H01L2224/48091 , H01L2224/48106 , H01L2224/48247 , H01L2224/49176 , H01L2924/1443
Abstract: In some embodiments, the present application provides an integrated chip. The integrated chip includes a chip comprising a semiconductor device. A shielding structure abuts the chip. The shielding structure comprises a first horizontal region adjacent to a first horizontal surface of the chip. The first horizontal region comprises a first multilayer structure comprising a first dielectric layer and two or more metal layers. The first dielectric layer is disposed between the two or more metal layers.
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公开(公告)号：US20230290748A1
公开(公告)日：2023-09-14
申请号：US17841112
申请日：2022-06-15
Inventor： Harry-Hak-Lay Chuang , Wei Cheng Wu , Wen-Tuo Huang , Yu-Ling Hsu , Pai Chi Chou , Ya-Chi Hung
IPC: H01L23/00 , H01L25/065 , H01L25/18 , H01L25/00
CPC classification number: H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2924/1431 , H01L2924/1434
Abstract: A semiconductor package includes a first wafer comprising a first substrate, a first device structure, and a first bonding layer having a pattern of first bonding pads. The first bonding layer is disposed over the first substrate and the first device structure. The semiconductor package includes a second wafer comprising a second substrate, a second device structure, and a second bonding layer having a pattern of second bonding pads. The second bonding layer is disposed over the first bonding layer. The second device structure is disposed over the second bonding layer. The second substrate is disposed over the second device structure. The first bonding pads are each aligned with a corresponding one of the second bonding pads. The first device structure is electrically coupled to the second device structure, through at least one of the first bonding pads and at least one of the second bonding pads.
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