公开(公告)号：US11889769B2

公开(公告)日：2024-01-30

申请号：US17872520

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H10N50/80 ,  H01F10/32 ,  H01F41/34 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/01 ,  G11C11/16

CPC classification number: H10N50/80 ,  H01F10/3254 ,  H01F41/34 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/22 ,  H10N50/01 ,  G11C11/161

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate. The top electrode has a width that decreases as a height of the top electrode increases. A bottom electrode via couples the bottom electrode to a lower interconnect. An upper interconnect structure is coupled to the top electrode. The upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode. The vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.

公开(公告)号：US20210351345A1

公开(公告)日：2021-11-11

申请号：US17381635

申请日：2021-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Chen-Pin Hsu ,  Hung Cho Wang ,  Wen-Chun You ,  Sheng-Chang Chen ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L23/528 ,  H01F41/32 ,  H01L21/768 ,  H01L23/522

Abstract: Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.

公开(公告)号：US11043531B2

公开(公告)日：2021-06-22

申请号：US16689918

申请日：2019-11-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Alexander Kalnitsky ,  Sheng-Huang Huang ,  Harry-Hak-Lay Chuang ,  Jiunyu Tsai ,  Hung Cho Wang

IPC: H01L27/00 ,  H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16 ,  H01L43/12

Abstract: The present disclosure provides a semiconductor structure having a memory region. The semiconductor structure includes an Nth metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the Nth metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs; and an (N+M)th metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.

公开(公告)号：US12167614B2

公开(公告)日：2024-12-10

申请号：US17533385

申请日：2021-11-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.

公开(公告)号：US20220359815A1

公开(公告)日：2022-11-10

申请号：US17872520

申请日：2022-07-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L43/12 ,  H01L23/528 ,  H01L21/768 ,  H01F41/34 ,  H01L23/522

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate. The top electrode has a width that decreases as a height of the top electrode increases. A bottom electrode via couples the bottom electrode to a lower interconnect. An upper interconnect structure is coupled to the top electrode. The upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode. The vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.

公开(公告)号：US20220093684A1

公开(公告)日：2022-03-24

申请号：US17533385

申请日：2021-11-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.

公开(公告)号：US11678493B2

公开(公告)日：2023-06-13

申请号：US17353521

申请日：2021-06-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Alexander Kalnitsky ,  Sheng-Huang Huang ,  Harry-Hak-Lay Chuang ,  Jiunyu Tsai ,  Hung Cho Wang

IPC: H01L27/00 ,  H10B61/00 ,  H01F10/32 ,  H01F41/34 ,  G11C11/16 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/20 ,  G11C11/161 ,  H01F10/3254 ,  H01F41/34 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H01F10/329

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes an Nth metal layer in a memory region and a periphery region, the periphery region spanning a wider area than the memory region, a plurality of magnetic tunneling junctions (MTJs) over the Nth metal layer, the plurality of MTJs having at least one of mixed pitches and mixed sizes, a top electrode via over each of the plurality of MTJs; and an (N+M)th metal layer over the plurality of MTJs. A method for manufacturing the semiconductor structure is also disclosed.

公开(公告)号：US09780301B1

公开(公告)日：2017-10-03

申请号：US15130216

申请日：2016-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Harry-Hak-Lay Chuang ,  Jiunyu Tsai ,  Hung Cho Wang ,  Tsun Chung Tu

IPC: H01L21/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.

公开(公告)号：US10109790B2

公开(公告)日：2018-10-23

申请号：US15683148

申请日：2017-08-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Harry-Hak-Lay Chuang ,  Jiunyu Tsai ,  Hung Cho Wang ,  Tsun Chung Tu

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/02

Abstract: A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.

公开(公告)号：US20240381670A1

公开(公告)日：2024-11-14

申请号：US18782345

申请日：2024-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80

Abstract: Some embodiments relate to an integrated circuit including a magnetoresistive random-access memory (MRAM) cell. The integrated circuit includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes metal layers that are stacked over one another with dielectric layers disposed between. The metal layers include a lower metal layer and an upper metal layer disposed over the lower metal layer. A bottom electrode is disposed over and in electrical contact with the lower metal layer. A magnetic tunneling junction (MTJ) is disposed over an upper surface of bottom electrode. A top electrode is disposed over an upper surface of the MTJ. A sidewall spacer surrounds an outer periphery of the top electrode. Less than an entirety of a top electrode surface is in direct electrical contact with a metal via connected to the upper metal layer.