公开(公告)号：US20150228790A1

公开(公告)日：2015-08-13

申请号：US14688720

申请日：2015-04-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Pin Hsu ,  Harry Chuang ,  Kong-Beng Thei

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.

摘要翻译： 本公开提供了一种制造半导体器件的方法，该方法包括在硅衬底上形成栅极叠层，在栅极叠层的侧壁上形成虚设间隔物，各向同性地蚀刻硅衬底以在栅叠层的任一侧上形成凹陷区，形成 在所述凹部区域中的半导体材料，所述半导体材料与所述硅衬底不同，去除所述虚设衬垫，在所述栅极堆叠和所述半导体材料上形成具有氧化物 - 氮化物 - 氧化物构造的间隔层，并蚀刻所述间隔层以形成 栅极叠层的侧壁上的栅极间隔物。

公开(公告)号：US20210351345A1

公开(公告)日：2021-11-11

申请号：US17381635

申请日：2021-07-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Chen-Pin Hsu ,  Hung Cho Wang ,  Wen-Chun You ,  Sheng-Chang Chen ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC分类号： H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L23/528 ,  H01F41/32 ,  H01L21/768 ,  H01L23/522

摘要： Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.

公开(公告)号：US20220246843A1

公开(公告)日：2022-08-04

申请号：US17725842

申请日：2022-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Chen-Pin Hsu ,  Hung Cho Wang ,  Wen-Chun You ,  Sheng-Chang Chen ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC分类号： H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L23/528 ,  H01F41/32 ,  H01L21/768 ,  H01L23/522

摘要： Some embodiments relate to a semiconductor structure having a magnetic tunnel junction (MTJ) on a substrate and a top electrode on the MTJ. A first segment of a top surface of the top electrode adjacent to a first sidewall of the top electrode is different from a second segment of the top surface of the top electrode adjacent to a second sidewall of the top electrode. A sidewall spacer comprises a first spacer on the first sidewall of the top electrode and a second spacer on the second sidewall of the top electrode. A first surface of the first spacer comprises a first curve and a second surface of the second spacer comprises a second curve. A dielectric layer is around the MTJ and top electrode.

公开(公告)号：US09419099B2

公开(公告)日：2016-08-16

申请号：US14688720

申请日：2015-04-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chen-Pin Hsu ,  Harry Chuang ,  Kong-Beng Thei

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/49 ,  H01L29/51

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The present disclosure provides a method for fabricating a semiconductor device that includes forming a gate stack over a silicon substrate, forming dummy spacers on sidewalls of the gate stack, isotropically etching the silicon substrate to form recess regions on either side of the gate stack, forming a semiconductor material in the recess regions, the semiconductor material being different from the silicon substrate, removing the dummy spacers, forming spacer layers having an oxide-nitride-oxide configuration over the gate stack and the semiconductor material, and etching the spacer layers to form gate spacers on the sidewalls of the gate stack.