公开(公告)号：US20220359815A1

公开(公告)日：2022-11-10

申请号：US17872520

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC分类号： H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L43/12 ,  H01L23/528 ,  H01L21/768 ,  H01F41/34 ,  H01L23/522

摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate. The top electrode has a width that decreases as a height of the top electrode increases. A bottom electrode via couples the bottom electrode to a lower interconnect. An upper interconnect structure is coupled to the top electrode. The upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode. The vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.

公开(公告)号：US20240090340A1

公开(公告)日：2024-03-14

申请号：US18511133

申请日：2023-11-16

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC分类号： H10N50/80 ,  H01F10/32 ,  H01F41/34 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/01

CPC分类号： H10N50/80 ,  H01F10/3254 ,  H01F41/34 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/22 ,  H10N50/01 ,  G11C11/161

摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a memory device surrounded by a dielectric structure disposed over a substrate. The memory device includes a data storage structure disposed between a bottom electrode and a top electrode. A bottom electrode via couples the bottom electrode to a lower interconnect. A top electrode via couples the top electrode to an upper interconnect. A bottommost surface of the top electrode via is directly over the top electrode and has a first width that is smaller than a second width of a bottommost surface of the bottom electrode via.

公开(公告)号：US20220246843A1

公开(公告)日：2022-08-04

申请号：US17725842

申请日：2022-04-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Chen-Pin Hsu ,  Hung Cho Wang ,  Wen-Chun You ,  Sheng-Chang Chen ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC分类号： H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L23/528 ,  H01F41/32 ,  H01L21/768 ,  H01L23/522

摘要： Some embodiments relate to a semiconductor structure having a magnetic tunnel junction (MTJ) on a substrate and a top electrode on the MTJ. A first segment of a top surface of the top electrode adjacent to a first sidewall of the top electrode is different from a second segment of the top surface of the top electrode adjacent to a second sidewall of the top electrode. A sidewall spacer comprises a first spacer on the first sidewall of the top electrode and a second spacer on the second sidewall of the top electrode. A first surface of the first spacer comprises a first curve and a second surface of the second spacer comprises a second curve. A dielectric layer is around the MTJ and top electrode.

公开(公告)号：US11889769B2

公开(公告)日：2024-01-30

申请号：US17872520

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ming-Che Ku ,  Harry-Hak-Lay Chuang ,  Hung Cho Wang ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC分类号： H10N50/80 ,  H01F10/32 ,  H01F41/34 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/01 ,  G11C11/16

CPC分类号： H10N50/80 ,  H01F10/3254 ,  H01F41/34 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/22 ,  H10N50/01 ,  G11C11/161

摘要： The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a magnetic tunnel junction arranged between a bottom electrode and a top electrode and surrounded by a dielectric structure disposed over a substrate. The top electrode has a width that decreases as a height of the top electrode increases. A bottom electrode via couples the bottom electrode to a lower interconnect. An upper interconnect structure is coupled to the top electrode. The upper interconnect structure has a vertically extending surface that is disposed laterally between first and second outermost sidewalls of the upper interconnect structure and along a sidewall of the top electrode. The vertically extending surface and the first outermost sidewall are connected to a bottom surface of the upper interconnect structure that is vertically below a top of the top electrode.

公开(公告)号：US20210351345A1

公开(公告)日：2021-11-11

申请号：US17381635

申请日：2021-07-21

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Harry-Hak-Lay Chuang ,  Chen-Pin Hsu ,  Hung Cho Wang ,  Wen-Chun You ,  Sheng-Chang Chen ,  Tsun Chung Tu ,  Jiunyu Tsai ,  Sheng-Huang Huang

IPC分类号： H01L43/12 ,  H01L43/02 ,  H01F10/32 ,  H01L27/22 ,  H01L23/528 ,  H01F41/32 ,  H01L21/768 ,  H01L23/522

摘要： Some embodiments relate to an integrated chip having a memory cell overlying a substrate and comprising a top electrode. A top electrode via overlies the top electrode. A width of an upper surface of the top electrode via is greater than a width of an upper surface of the top electrode. A conductive via overlies the top electrode via. A width of an upper surface of the conductive via is greater than the width of the upper surface of the top electrode via.

公开(公告)号：US09780301B1

公开(公告)日：2017-10-03

申请号：US15130216

申请日：2016-04-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Harry-Hak-Lay Chuang ,  Jiunyu Tsai ,  Hung Cho Wang ,  Tsun Chung Tu

IPC分类号： H01L21/00 ,  H01L43/12 ,  H01L43/02 ,  H01L43/08

CPC分类号： H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08

摘要： A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.

公开(公告)号：US10109790B2

公开(公告)日：2018-10-23

申请号：US15683148

申请日：2017-08-22

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Harry-Hak-Lay Chuang ,  Jiunyu Tsai ,  Hung Cho Wang ,  Tsun Chung Tu

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L43/02

摘要： A method for manufacturing a semiconductor structure is disclosed. The method includes: providing a substrate; forming an MRAM structure over the substrate; forming a first dielectric layer over the MRAM structure; forming a stop layer over the first dielectric layer; forming a second dielectric layer over the stop layer; and removing the second dielectric layer, the stop layer and at least a portion of the first dielectric layer through a planarization operation without exposing a top electrode of the MRAM structure. Associated methods are also disclosed.