Invention Publication
- Patent Title: STRUCTURE AND METHOD FOR VERTICAL TUNNELING FIELD EFFECT TRANSISTOR WITH LEVELED SOURCE AND DRAIN
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Application No.: US18432985Application Date: 2024-02-05
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Publication No.: US20240178303A1Publication Date: 2024-05-30
- Inventor: Harry-Hak-Lay Chuang , Yi-Ren Chen , Chi-Wen Liu , Chao-Hsiung Wang , Ming Zhu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- The original application number of the division: US13795240 2013.03.12
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/8234 ; H01L21/8238 ; H01L27/08 ; H01L27/092 ; H01L29/78

Abstract:
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.
Information query
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