公开(公告)号：US20180247913A1

公开(公告)日：2018-08-30

申请号：US15444130

申请日：2017-02-27

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC. ,  NATIONAL CHUNG HSING UNIVERSITY

Inventor： Ying-Ta CHIU ,  Shang-Kun HUANG ,  Yong-Da CHIU ,  Jenn-Ming SONG

IPC: H01L23/00

CPC classification number: H01L24/80 ,  H01L24/05 ,  H01L2224/80009 ,  H01L2224/80092 ,  H01L2224/8012 ,  H01L2224/80203

Abstract: The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a first metal contact and a second electronic component including a second metal contact, changing a lattice of the first metal contact, and bonding the first metal contact to the second metal contact under a predetermined pressure and a predetermined temperature.

公开(公告)号：US20170278814A1

公开(公告)日：2017-09-28

申请号：US15076831

申请日：2016-03-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Dao-Long CHEN ,  Ying-Ta CHIU ,  Ping-Feng YANG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US20190244909A1

公开(公告)日：2019-08-08

申请号：US15891305

申请日：2018-02-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yong-Da CHIU ,  Shiu-Chih WANG ,  Shang-Kun HUANG ,  Ying-Ta CHIU ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L23/532 ,  H01L23/00

CPC classification number: H01L23/53233 ,  H01L23/53238 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/161 ,  H05K2201/03 ,  H05K2201/09481

Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.

公开(公告)号：US20190148326A1

公开(公告)日：2019-05-16

申请号：US16247437

申请日：2019-01-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Dao-Long CHEN ,  Ying-Ta CHIU ,  Ping-Feng YANG

IPC: H01L23/00

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US20180114762A1

公开(公告)日：2018-04-26

申请号：US15299236

申请日：2016-10-20

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ying-Ta CHIU ,  Chiu-Wen LEE ,  Dao-Long CHEN ,  Po-Hsien SUNG ,  Ping-Feng YANG ,  Kwang-Lung LIN

IPC: H01L23/60 ,  H01L23/31 ,  H01L23/06 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/60 ,  H01L21/56 ,  H01L21/565 ,  H01L23/06 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/552 ,  H01L24/49 ,  H01L2224/48091

Abstract: A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is disposed on the substrate. The encapsulant covers the semiconductor element. The adhesion layer is disposed on the encapsulant. The metal cap is attached to the encapsulant by the adhesion layer, and the metal cap is conformal with the encapsulant.