公开(公告)号：US20220367304A1

公开(公告)日：2022-11-17

申请号：US17317770

申请日：2021-05-11

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Kuoching CHENG ,  Yuan-Feng CHIANG ,  Ya Fang CHAN ,  Wen-Long LU ,  Shih-Yu WANG

IPC分类号： H01L23/31 ,  H01L25/065 ,  H01L23/16 ,  H01L23/538 ,  H01L21/56

摘要： An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.

公开(公告)号：US20240249958A1

公开(公告)日：2024-07-25

申请号：US18099867

申请日：2023-01-20

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Ya Fang CHAN ,  Cong-Wei CHEN ,  Kuoching CHENG ,  Shih-Yu WANG

IPC分类号： H01L21/67 ,  H01L21/683

CPC分类号： H01L21/67092 ,  H01L21/6838

摘要： A method for manufacturing a semiconductor package and an apparatus for flattening a workpiece are provided. The method includes providing a panel over a stage, wherein the panel includes a lower surface facing the stage and an upper surface opposite to the lower surface; applying a first force to a first region of the upper surface of the panel along at least one direction from the panel toward the stage; and transferring the first force from the first region to a second region of the upper surface of the panel different from the first region.

公开(公告)号：US20210280565A1

公开(公告)日：2021-09-09

申请号：US17330240

申请日：2021-05-25

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien-Mei HUANG ,  Shih-Yu WANG ,  I-Ting LIN ,  Wen Hung HUANG ,  Yuh-Shan SU ,  Chih-Cheng LEE ,  Hsing Kuo TIEN

IPC分类号： H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528

摘要： A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US20230387092A1

公开(公告)日：2023-11-30

申请号：US18231767

申请日：2023-08-08

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien-Mei HUANG ,  Shih-Yu WANG ,  I-Ting LIN ,  Wen Hung HUANG ,  Yuh-Shan SU ,  Chih-Cheng LEE ,  Hsing Kuo TIEN

IPC分类号： H01L25/16 ,  H01L23/31 ,  H01L23/00 ,  H01L23/522 ,  H01L21/56 ,  H01L23/528

CPC分类号： H01L25/16 ,  H01L23/3171 ,  H01L23/315 ,  H01L23/3128 ,  H01L24/17 ,  H01L23/5226 ,  H01L21/563 ,  H01L23/5283 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L23/293

摘要： A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.

公开(公告)号：US20180337130A1

公开(公告)日：2018-11-22

申请号：US15596956

申请日：2017-05-16

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Chien Lin CHANG CHIEN ,  Chin-Li KAO ,  Shih-Yu WANG ,  Chang Chi LEE

IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L21/683

CPC分类号： H01L23/5384 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L2221/68345 ,  H01L2221/68359

摘要： A semiconductor package device includes a first interconnection structure, a non-silicon interposer and a first die. The first interconnection structure has a first pitch. The non-silicon interposer surrounds the first interconnection structure. The non-silicon interposer includes a second interconnection structure having a second pitch. The second pitch is larger than the first pitch. The first die is above the first interconnection structure and is electrically connected to the first interconnection structure.