公开(公告)号：US11955534B2

公开(公告)日：2024-04-09

申请号：US18077142

申请日：2022-12-07

Applicant: Intel Corporation

Inventor： Andrew W. Yeoh ,  Joseph Steigerwald ,  Jinhong Shin ,  Vinay Chikarmane ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78 ,  H01L49/02 ,  H10B10/00 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US20240088225A1

公开(公告)日：2024-03-14

申请号：US18508788

申请日：2023-11-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Hao Liu ,  Wen-Yen Chen ,  Li-Heng Chen ,  Li-Ting Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Ying-Lang Wang

IPC: H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

Abstract: A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

公开(公告)号：US20240047556A1

公开(公告)日：2024-02-08

申请号：US18381442

申请日：2023-10-18

Applicant: Intel Corporation

Inventor： Andrew W. YEOH ,  Joseph STEIGERWALD ,  Jinhong SHIN ,  Vinay CHIKARMANE ,  Christopher P. AUTH

IPC: H01L29/66 ,  H10B10/00 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H10B10/12 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7854 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

公开(公告)号：US20230402524A1

公开(公告)日：2023-12-14

申请号：US18447580

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Liang CHENG

IPC: H01L29/49 ,  H01L21/3065 ,  H01L29/78 ,  H01L29/423 ,  H01L27/06 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/4933 ,  H01L21/3065 ,  H01L29/7845 ,  H01L29/42392 ,  H01L29/785 ,  H01L27/0688 ,  H01L29/66795 ,  H01L29/0669 ,  H01L2029/7858

Abstract: A semiconductor device includes a multi-silicide structure comprising at least two conformal silicide layers. The multi-silicide structure may include a first conformal silicide layer on a source/drain, a second conformal silicide layer on the first conformal silicide layer, and a capping layer over the second conformal silicide layer. The semiconductor device includes a contact structure on the multi-silicide structure. The semiconductor device includes a dielectric material around the contact structure. In some implementations, a controller may determine etch process parameters to be used by an etch tool to perform an iteration of an atomic layer etch (ALE) process on the semiconductor device.

公开(公告)号：US11799015B2

公开(公告)日：2023-10-24

申请号：US17703884

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Tahir Ghani ,  Byron Ho ,  Michael L. Hattendorf ,  Christopher P. Auth

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/311 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/02 ,  H01L27/088 ,  H01L27/092 ,  H01L49/02 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/167 ,  H01L29/417 ,  H01L29/51 ,  H10B10/00 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, a method includes forming a plurality of fins and forming a plurality of gate structures over the plurality of fins. A dielectric material structure is formed between adjacent ones of the plurality of gate structures. A portion of a first of the plurality of gate structures is removed to expose a first portion of each of the plurality of fins, and a portion of a second of the plurality of gate structures is removed to expose a second portion of each of the plurality of fins. The exposed first portion of each of the plurality of fins is removed, but the exposed second portion of each of the plurality of fins is not removed.

公开(公告)号：US20230268440A1

公开(公告)日：2023-08-24

申请号：US17700530

申请日：2022-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Fang-Yun Liu ,  Chien-Tung Yue ,  Kuo-Liang Yeh ,  Mu-Kai Tsai ,  Jinn-Horng Lai ,  Cheng-Hsiung Chen

IPC: H01L29/78 ,  H01L27/092 ,  H01L23/58

CPC classification number: H01L29/7845 ,  H01L27/092 ,  H01L23/585

Abstract: A semiconductor device includes a substrate, a first transistor disposed on the substrate, a second transistor in proximity to the first transistor on the substrate, at least one interlayer dielectric layer covering the first transistor and the second transistor, a first stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the first transistor, and a second stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the second transistor.

公开(公告)号：US20230231028A1

公开(公告)日：2023-07-20

申请号：US18190221

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Jier Yang ,  Tai-Hsin Chiu

IPC: H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L29/513 ,  H01L29/4966 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/66545 ,  H01L29/7856 ,  H01L29/7845 ,  H01L27/0207 ,  H01L29/495 ,  H01L29/4983 ,  H01L21/82345

Abstract: A semiconductor device includes an active region spanning along a first direction. The semiconductor device includes a first elongated gate spanning along a second direction substantially perpendicular to the first direction. The first elongated gate includes a first portion that is disposed over the active region and a second portion that is not disposed over the active region. The first portion and the second portion include different materials. The semiconductor device includes a second elongated gate spanning along the second direction and separated from the first elongated gate in the first direction. The second elongated gate includes a third portion that is disposed over the active region and a fourth portion that is not disposed over the active region. The third portion and the fourth portion include different materials.

公开(公告)号：US11664439B2

公开(公告)日：2023-05-30

申请号：US17243476

申请日：2021-04-28

Applicant: Intel Corporation

Inventor： Subhash M. Joshi ,  Jeffrey S. Leib ,  Michael L. Hattendorf

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L21/762 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/165 ,  H01L29/417 ,  H01L21/033 ,  H01L21/28 ,  H01L21/285 ,  H01L21/308 ,  H01L21/8238 ,  H01L23/528 ,  H01L27/092 ,  H01L49/02 ,  H01L29/08 ,  H01L29/51 ,  H01L27/02 ,  H01L21/02 ,  H01L29/167 ,  H01L23/00

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0337 ,  H01L21/28247 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/3086 ,  H01L21/31105 ,  H01L21/31144 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53209 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/0922 ,  H01L27/0924 ,  H01L28/20 ,  H01L28/24 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/7843 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7854 ,  H10B10/12 ,  H01L21/0217 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7853 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A gate dielectric layer is over the top of the fin and laterally adjacent the sidewalls of the fin. A gate electrode is over the gate dielectric layer over the top of the fin and laterally adjacent the sidewalls of the fin. First and second semiconductor source or drain regions are adjacent the first and second sides of the gate electrode, respectively. First and second trench contact structures are over the first and second semiconductor source or drain regions, respectively, the first and second trench contact structures both comprising a U-shaped metal layer and a T-shaped metal layer on and over the entirety of the U-shaped metal layer.

公开(公告)号：US11664432B2

公开(公告)日：2023-05-30

申请号：US16556796

申请日：2019-08-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Dirk Utess ,  Zhixing Zhao ,  Dominik M. Kleimaier ,  Irfan A. Saadat ,  Florent Ravaux

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L27/092 ,  H01L29/401 ,  H01L29/7845

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

公开(公告)号：US10014410B2

公开(公告)日：2018-07-03

申请号：US15505563

申请日：2014-12-02

Applicant: Renesas Electronics Corporation

Inventor： Tadashi Yamaguchi

IPC: H01L21/8238 ,  H01L29/78 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66 ,  H01L21/285

CPC classification number: H01L29/7845 ,  H01L21/28518 ,  H01L21/28568 ,  H01L27/115 ,  H01L27/11568 ,  H01L27/11573 ,  H01L28/00 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545

Abstract: A silicide layer on a gate electrode of a MONOS memory is prevented from being disconnected, and a property of a MISFET is improved. As means for that, when a memory cell and a MISFET formed by so-called gate-last process are mixedly mounted, a silicide layer on a source/drain region is formed by a salicide process with relatively high temperature heat treatment, and then, a silicide layer is formed on each of the control gate electrode and the memory gate electrode of the memory cell by a salicide process with relatively low temperature heat treatment.