公开(公告)号：US20240321751A1

公开(公告)日：2024-09-26

申请号：US18654111

申请日：2024-05-03

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L23/532 ,  H01L21/3215 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53242 ,  H01L21/3215 ,  H01L21/76883 ,  H01L23/5226

摘要： A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

公开(公告)号：US20240088225A1

公开(公告)日：2024-03-14

申请号：US18508788

申请日：2023-11-14

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Su-Hao Liu ,  Wen-Yen Chen ,  Li-Heng Chen ,  Li-Ting Wang ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Ying-Lang Wang

IPC分类号： H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76814 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0924 ,  H01L29/161 ,  H01L29/66507 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L2029/7858

摘要： A method includes forming a gate stack on a first portion of a semiconductor substrate, removing a second portion of the semiconductor substrate on a side of the gate stack to form a recess, growing a semiconductor region starting from the recess, implanting the semiconductor region with an impurity, and performing a melt anneal on the semiconductor region. At least a portion of the semiconductor region is molten during the melt anneal.

公开(公告)号：US20230369055A1

公开(公告)日：2023-11-16

申请号：US18359735

申请日：2023-07-26

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Meng-Han Chou ,  Kuan-Yu Yeh ,  Wei-Yip Loh ,  Hung-Hsu Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L21/285 ,  H01L29/45 ,  H01L21/768 ,  H01L21/02 ,  H01L21/3115 ,  H01L21/311

CPC分类号： H01L21/28518 ,  H01L29/45 ,  H01L21/76814 ,  H01L21/02063 ,  H01L21/76895 ,  H01L21/31155 ,  H01L21/31111 ,  H01L21/76805

摘要： The present disclosure provides a method to enlarge the process window for forming a source/drain contact. The method may include receiving a workpiece that includes a source/drain feature exposed in a source/drain opening defined between two gate structures, conformally depositing a dielectric layer over sidewalls of the source/drain opening and a top surface of the source/drain feature, anisotropically etching the dielectric layer to expose the source/drain feature, performing an implantation process to the dielectric layer, and after the performing of the implantation process, performing a pre-clean process to the workpiece. The implantation process includes a non-zero tilt angle.

公开(公告)号：US20230253243A1

公开(公告)日：2023-08-10

申请号：US18190297

申请日：2023-03-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Ju Chen ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Meng-Han Chou

IPC分类号： H01L21/768 ,  H01L29/78 ,  H01L23/522

CPC分类号： H01L21/76802 ,  H01L29/785 ,  H01L23/5226 ,  H01L21/76877

摘要： A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

公开(公告)号：US20230197852A1

公开(公告)日：2023-06-22

申请号：US18174045

申请日：2023-02-24

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Su-Hao Liu ,  Kuo-Ju Chen ,  Wen-Yen Chen ,  Ying-Lang Wang ,  Liang-Yin Chen ,  Li-Ting Wang ,  Huicheng Chang

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/324 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02

CPC分类号： H01L29/785 ,  H01L21/76829 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/6681 ,  H01L21/02694 ,  H01L21/823864

摘要： Embodiments disclosed herein relate to using an implantation process and a melting anneal process performed on a nanosecond scale to achieve a high surface concentration (surface pile up) dopant profile and a retrograde dopant profile simultaneously. In an embodiment, a method includes forming a source/drain structure in an active area on a substrate, the source/drain structure including a first region comprising germanium, implanting a first dopant into the first region of the source/drain structure to form an amorphous region in at least the first region of the source/drain structure, implanting a second dopant into the amorphous region containing the first dopant, and heating the source/drain structure to liquidize and convert at least the amorphous region into a crystalline region, the crystalline region containing the first dopant and the second dopant.

公开(公告)号：US20230016619A1

公开(公告)日：2023-01-19

申请号：US17684876

申请日：2022-03-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tien-Shun Chang ,  Yu-Kang Liu ,  Su-Hao Liu ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01J37/317 ,  H01J37/304

摘要： A method includes moving a plurality of sensors along a translation path with respect to an ion beam, acquiring sensor signals produced by the plurality of sensors, converting the acquired sensor signals into a data set representative of a two-dimensional (2D) profile of the ion beam, generating a plurality of first one-dimensional (1D) profiles of the ion beam from the data set, generating a plurality of second 1D profiles of the ion beam by spatially inverting each of the plurality of first 1D profiles, generating a plurality of third 1D profiles of the ion beam by superposing first current density values of each of the plurality of first 1D profiles with second current density values of a corresponding one of the plurality of second 1D profiles and determining whether to continue an implantation process with the ion beam in accordance with the plurality of third 1D profiles.

公开(公告)号：US20220367632A1

公开(公告)日：2022-11-17

申请号：US17872452

申请日：2022-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC分类号： H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

摘要： The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20210335719A1

公开(公告)日：2021-10-28

申请号：US17171320

申请日：2021-02-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3215

摘要： A semiconductor device includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants. The dopants are bonded to the noble metal material.

公开(公告)号：US20210327818A1

公开(公告)日：2021-10-21

申请号：US17171210

申请日：2021-02-09

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Kuo-Ju Chen ,  Chun-Hsien Huang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

摘要： A connecting structure includes a first dielectric layer disposed over a substrate and a conductive feature, a doped dielectric layer disposed over the first dielectric layer, a first metal portion disposed in the first dielectric layer and in contact with the conductive feature, and a doped metal portion disposed over the first metal portion. The first metal portion and the doped metal portion include a same noble metal material. The doped dielectric layer and the doped metal portion include same dopants.

公开(公告)号：US20210111035A1

公开(公告)日：2021-04-15

申请号：US17107558

申请日：2020-11-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Su-Hao Liu ,  Tsan-Chun Wang ,  Liang-Yin Chen ,  Jing-Huei Huang ,  Lun-Kuang Tan ,  Huicheng Chang

IPC分类号： H01L21/3115 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/311 ,  H01L29/66

摘要： In a gate last metal gate process for forming a transistor, a dielectric layer is formed over an intermediate transistor structure, the intermediate structure including a dummy gate electrode, typically formed of polysilicon. Various processes, such as patterning the polysilicon, planarizing top layers of the structure, and the like can remove top portions of the dielectric layer, which can result in decreased control of gate height when a metal gate is formed in place of the dummy gate electrode, decreased control of fin height for finFETs, and the like. Increasing the resistance of the dielectric layer to attack from these processes, such as by implanting silicon or the like into the dielectric layer before such other processes are performed, results in less removal of the top surface, and hence improved control of the resulting structure dimensions and performance.