公开(公告)号：US20220181451A1

公开(公告)日：2022-06-09

申请号：US17651843

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsan-Chun Wang ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L29/40 ,  H01L29/45 ,  H01L21/3115 ,  H01L21/033 ,  H01L21/285

摘要： A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.

公开(公告)号：US11031293B2

公开(公告)日：2021-06-08

申请号：US16656209

申请日：2019-10-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tsan-Chun Wang ,  Chun-Feng Nieh ,  Chiao-Ting Tai

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/3115 ,  H01L21/265 ,  H01L29/51 ,  H01L21/28

摘要： A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

公开(公告)号：US11011428B2

公开(公告)日：2021-05-18

申请号：US16656247

申请日：2019-10-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Tsan-Chun Wang ,  Chun-Feng Nieh ,  Chiao-Ting Tai

IPC分类号： H01L21/8234 ,  H01L21/265 ,  H01L21/3115 ,  H01L27/088 ,  H01L29/51 ,  H01L21/28

摘要： A method for fabricating a semiconductor device includes forming a fin extending along a first direction on a semiconductor substrate and forming a sacrificial gate electrode structure extending along a second direction substantially perpendicular to the first direction over the fin. The sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer. Opposing gate sidewall spacers are formed extending along the second direction, on opposing sides of the sacrificial gate electrode layer. The sacrificial gate electrode layer is removed to form a gate space. Fluorine is implanted into the gate sidewall spacers after removing the gate electrode layer by performing a first fluorine implantation. The sacrificial gate dielectric layer is removed and a high-k gate dielectric layer is formed in the gate space. Fluorine is implanted into the gate sidewall spacers and the fin after forming the high-k gate dielectric layer by performing a second fluorine implantation.

公开(公告)号：US20200279846A1

公开(公告)日：2020-09-03

申请号：US16852564

申请日：2020-04-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Hsiung Tsai ,  Ziwei Fang ,  Tsan-Chun Wang ,  Kei-Wei Chen

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/306 ,  H01L29/08 ,  H01L29/06

摘要： A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.

公开(公告)号：US10249530B2

公开(公告)日：2019-04-02

申请号：US15473166

申请日：2017-03-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsan-Chun Wang ,  De-Wei Yu ,  Ziwei Fang ,  Yi-Fan Chen

IPC分类号： H01L29/78 ,  H01L21/768 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/324 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8234 ,  H01L23/522 ,  H01L27/088 ,  H01L29/417 ,  H01L21/02 ,  H01L23/48

摘要： A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.

公开(公告)号：US20180166341A1

公开(公告)日：2018-06-14

申请号：US15376719

申请日：2016-12-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Ling CHAN ,  Tsan-Chun Wang ,  Liang-Yin Chen ,  Huicheng Chang

IPC分类号： H01L21/8234 ,  H01L21/84 ,  H01L29/66 ,  H01L21/223

CPC分类号： H01L21/823431 ,  H01L21/2236 ,  H01L21/823418 ,  H01L29/6656 ,  H01L29/66803

摘要： A plasma doping process provides conformal doping profiles for lightly doped source/drain regions in fins, and reduces the plasma doping induced fin height loss. The plasma doping process overcomes the limitations caused by traditional plasma doping processes in fin structures that feature aggressive aspect ratios and tights pitches. Semiconductor devices with conformal lightly doped S/D regions and reduced fin height loss demonstrate reduced parallel resistance (Rp) and improved transistor performance.

公开(公告)号：US09748363B2

公开(公告)日：2017-08-29

申请号：US14608147

申请日：2015-01-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chun Hsiung Tsai ,  Tsan-Chun Wang

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/66 ,  H01L21/225 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78 ,  H01L21/84 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324

CPC分类号： H01L29/66803 ,  H01L21/2256 ,  H01L21/2658 ,  H01L21/266 ,  H01L21/324 ,  H01L21/845 ,  H01L29/1033 ,  H01L29/1095 ,  H01L29/16 ,  H01L29/785 ,  H01L29/7851

摘要： A method for manufacturing a semiconductor device includes forming a fin structure having a top surface and side surfaces. A mask layer is disposed over the top surface. A doping support layer is formed to cover part of the fin structure. A first impurity is introduced into a first region of the fin structure covered by the doping support layer, by implanting the first impurity into the doping support layer so that the implanted first impurity is introduced into the first region of the fin structure through the side surfaces.

公开(公告)号：US09680014B2

公开(公告)日：2017-06-13

申请号：US14690331

申请日：2015-04-17

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chun Hsiung Tsai ,  Tsan-Chun Wang

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66 ,  H01L21/265 ,  H01L21/02

CPC分类号： H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/26506 ,  H01L21/26513 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66636 ,  H01L29/66795

摘要： A p-type semiconductor Fin FET device includes a fin structure disposed over a substrate. The fin structure includes a channel layer. The Fin FET device also includes a gate structure including a gate electrode layer and a gate dielectric layer, covering a portion of the fin structure. Side-wall insulating layers are disposed over both main sides of the gate electrode layer. The Fin FET device includes a source and a drain, each including a stressor layer disposed in a recess formed by removing the fin structure not covered by the gate structure. The stressor layer includes a first stressor layer and a second stressor layer formed in this order. In the source, an interface between the first stressor layer and the channel layer is located under one of the side-wall insulating layers closer to the source or the gate electrode.

公开(公告)号：US09537010B2

公开(公告)日：2017-01-03

申请号：US14613663

申请日：2015-02-04

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Tsan-Chun Wang ,  Ziwei Fang ,  Chien-Tai Chan ,  Da-Wen Lin ,  Huicheng Chang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/266 ,  H01L21/324

CPC分类号： H01L29/7856 ,  H01L21/2253 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66795

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a doped region in an upper portion of the substrate. The doped region is doped with first dopants of a first conduction type. The semiconductor device structure includes one fin structure over the substrate. A first dopant concentration of the doped region exposed by the fin structure is greater than a second dopant concentration of the doped region covered by the fin structure. The semiconductor device structure includes an isolation layer over the substrate and at two opposite sides of the fin structure. The semiconductor device structure includes a gate over the isolation layer and the fin structure.

摘要翻译： 提供半导体器件结构。 半导体器件结构包括在衬底的上部具有掺杂区的衬底。 掺杂区域掺杂有第一导电类型的第一掺杂剂。 半导体器件结构包括在衬底上的一个鳍结构。 通过鳍结构暴露的掺杂区域的第一掺杂剂浓度大于由鳍结构覆盖的掺杂区域的第二掺杂剂浓度。 半导体器件结构包括在衬底上并在鳍结构的两个相对侧的隔离层。 半导体器件结构包括隔离层上的栅极和鳍结构。

公开(公告)号：US20220310405A1

公开(公告)日：2022-09-29

申请号：US17838524

申请日：2022-06-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Tsan-Chun Wang ,  Chun-Feng Nieh

IPC分类号： H01L21/3215 ,  H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66 ,  C23C14/48 ,  H01J37/317 ,  H01L21/3115 ,  H01L21/02 ,  H01L21/28

摘要： A semiconductor device and method of manufacture are provided. In some embodiments a divergent ion beam is utilized to implant ions into a capping layer, wherein the capping layer is located over a first metal layer, a dielectric layer, and an interfacial layer over a semiconductor fin. The ions are then driven from the capping layer into one or more of the first metal layer, the dielectric layer, and the interfacial layer.