公开(公告)号：US20240258096A1

公开(公告)日：2024-08-01

申请号：US18635270

申请日：2024-04-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ru-Shang Hsiao ,  Chun Hsiung Tsai ,  Clement Hsingjen Wann

IPC分类号： H01L21/02 ,  B08B3/08 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535

CPC分类号： H01L21/02074 ,  B08B3/08 ,  H01L21/31111 ,  H01L21/76805 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76883 ,  H01L21/76889 ,  H01L21/76895 ,  H01L23/535

摘要： A semiconductor structure includes a substrate, a conductive feature over the substrate, a dielectric layer over the conductive feature and the substrate, and a structure disposed over and electrically connected to the conductive feature. The structure is partially surrounded by the dielectric layer and includes a first metal-containing layer and a second metal-contain layer surrounded by the first metal-containing layer. The first and the second metal-containing layers include different materials. A lower portion of the first metal-containing layer includes a transition metal or a transition metal nitride and an upper portion of the first metal-containing layer includes a transition metal fluoride or a transition metal chloride.

公开(公告)号：US11973126B2

公开(公告)日：2024-04-30

申请号：US18308213

申请日：2023-04-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Shahaji B. More ,  Chun Hsiung Tsai

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/762

CPC分类号： H01L29/66795 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/785 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78696 ,  H01L21/76224 ,  H01L29/66545

摘要： The present disclosure is directed to methods for the fabrication of gate-all-around (GAA) field effect transistors (FETs) with low power consumption. The method includes depositing a first and a second epitaxial layer on a substrate and etching trench openings in the first and second epitaxial layers and the substrate. The method further includes removing, through the trench openings, portions of the first epitaxial layer to form a gap between the second epitaxial layer and the substrate and depositing, through the trench openings, a first dielectric to fill the gap and form an isolation structure. In addition, the method includes depositing a second dielectric in the trench openings to form trench isolation structures and forming a transistor structure on the second epitaxial layer.

公开(公告)号：US11837507B2

公开(公告)日：2023-12-05

申请号：US17811651

申请日：2022-07-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shahaji B. More ,  Chandrashekhar Prakash Savant ,  Chun Hsiung Tsai

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49

CPC分类号： H01L21/82385 ,  H01L21/28088 ,  H01L21/32134 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

摘要： A semiconductor device and a method of forming the same are provided. A method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed over the gate dielectric layer in the opening. A first protective layer is formed over the first work function layer in the opening. A first etch process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.

公开(公告)号：US20230377995A1

公开(公告)日：2023-11-23

申请号：US18366871

申请日：2023-08-08

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Shahaji B. More ,  Chandrashekhar Prakash Savant ,  Chun Hsiung Tsai

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49

CPC分类号： H01L21/82385 ,  H01L21/823821 ,  H01L21/28088 ,  H01L21/32134 ,  H01L29/7851 ,  H01L29/66795 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

摘要： A semiconductor device and a method of forming the same are provided. A method includes forming a sacrificial gate over an active region of a substrate. The sacrificial gate is removed to form an opening. A gate dielectric layer is formed on sidewalls and a bottom of the opening. A first work function layer is formed over the gate dielectric layer in the opening. A first protective layer is formed over the first work function layer in the opening. A first etch process is performed to widen an upper portion of the opening. The opening is filled with a conductive material.

公开(公告)号：US20220285161A1

公开(公告)日：2022-09-08

申请号：US17664325

申请日：2022-05-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd

发明人： Kuo-Feng Yu ,  Chun Hsiung Tsai ,  Jian-Hao Chen ,  Hoong Shing Wong ,  Chih-Yu Hsu

IPC分类号： H01L21/28 ,  H01L21/033 ,  H01L21/311 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/092

摘要： A method includes forming a first gate dielectric and a second gate dielectric over a first semiconductor region and a second semiconductor region, respectively, depositing a lanthanum-containing layer including a first portion and a second portion overlapping the first gate dielectric and the second gate dielectric, respectively, and depositing a hard mask including a first portion and a second portion overlapping the first portion and the second portion of the lanthanum-containing layer, respectively. The hard mask is free from both of titanium and tantalum. The method further includes forming a patterned etching mask to cover the first portion of the hard mask, with the second portion of the hard mask being exposed, removing the second portion of the hard mask and the second portion of the lanthanum-containing layer, and performing an anneal to drive lanthanum in the first portion of the lanthanum-containing layer into the first gate dielectric.

公开(公告)号：US11316046B2

公开(公告)日：2022-04-26

申请号：US16933626

申请日：2020-07-20

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Shahaji B. More ,  Chun Hsiung Tsai

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/24 ,  H01L29/267 ,  H01L29/423 ,  H01L29/786

摘要： In a method of manufacturing a semiconductor device, an upper fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed over a lower fin structure, a sacrificial gate structure is formed over the upper fin structure, a source/drain region of the upper fin structure, which is not covered by the sacrificial gate structure, is etched thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, an inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers, and a source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. In etching the source/drain region, a part of the lower fin structure is also etched to form a recess, in which a (111) surface is exposed.

公开(公告)号：US11211455B2

公开(公告)日：2021-12-28

申请号：US16932924

申请日：2020-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun Hsiung Tsai ,  Wei-Yuan Lu ,  Chien-Tai Chan ,  Wei-Yang Lee ,  Da-Wen Lin

IPC分类号： H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L29/16 ,  H01L29/32 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165

摘要： Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

公开(公告)号：US10991800B2

公开(公告)日：2021-04-27

申请号：US16421036

申请日：2019-05-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun Hsiung Tsai ,  Ya-Yun Cheng ,  Shahaji B. More ,  Cheng-Yi Peng ,  Wei-Yang Lee ,  Kuo-Feng Yu ,  Yen-Ming Chen ,  Jian-Hao Chen

IPC分类号： H01L29/08 ,  H01L21/265 ,  H01L29/66 ,  H01L21/306 ,  H01L29/167 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  H01L29/36 ,  H01L21/266 ,  H01L29/165

摘要： A semiconductor device includes a substrate, an isolation structure over the substrate, a fin over the substrate and the isolation structure, a gate structure engaging a first portion of the fin, first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin, source/drain (S/D) features adjacent to the first sidewall spacers, and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers and the second portion of the fin include a same dopant.

公开(公告)号：US10923595B2

公开(公告)日：2021-02-16

申请号：US15908265

申请日：2018-02-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Yi Peng ,  Carlos H. Diaz ,  Chun Hsiung Tsai ,  Yu-Ming Lin

IPC分类号： H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/36 ,  H01L29/167 ,  H01L29/165

摘要： A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1−x−yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.

公开(公告)号：US20200350430A1

公开(公告)日：2020-11-05

申请号：US16933255

申请日：2020-07-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun Hsiung Tsai ,  Sheng-Wen Yu ,  Ziwei Fang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L29/165

摘要： A method includes forming a first channel region and a first gate structure formed over the first channel region. A first source/drain region is formed adjacent the first channel region and the first source/drain region includes a crystalline structure doped with a first dopant. A first silicide is formed over the first source/drain region. The first source/drain region includes a first concentration of the first dopant between 2.0×1021 atoms per centimeter cubed and 4.0×1021 atoms per centimeter cubed at a depth of 8 to 10 nanometers.