公开(公告)号：US20230268440A1

公开(公告)日：2023-08-24

申请号：US17700530

申请日：2022-03-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Yu Yang ,  Fang-Yun Liu ,  Chien-Tung Yue ,  Kuo-Liang Yeh ,  Mu-Kai Tsai ,  Jinn-Horng Lai ,  Cheng-Hsiung Chen

IPC: H01L29/78 ,  H01L27/092 ,  H01L23/58

CPC classification number: H01L29/7845 ,  H01L27/092 ,  H01L23/585

Abstract: A semiconductor device includes a substrate, a first transistor disposed on the substrate, a second transistor in proximity to the first transistor on the substrate, at least one interlayer dielectric layer covering the first transistor and the second transistor, a first stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the first transistor, and a second stress-inducing dummy metal pattern disposed on the at least one interlayer dielectric layer and directly above the second transistor.

公开(公告)号：US10475738B2

公开(公告)日：2019-11-12

申请号：US15391822

申请日：2016-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kung-Hong Lee ,  Mu-Kai Tsai ,  Chung-Hsing Lin

IPC: H01L23/522 ,  H01L49/02 ,  H01L27/088 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78

Abstract: A semiconductor device preferably includes: a first metal-oxide semiconductor (MOS) transistor on a substrate; a first ferroelectric (FE) layer connected to the first MOS transistor; a second MOS transistor on the substrate; and a second FE layer connected to the second MOS transistor. Preferably, the first FE layer and the second FE layer include different capacitance.

公开(公告)号：US20190318964A1

公开(公告)日：2019-10-17

申请号：US16297702

申请日：2019-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Han-Tsun Wang ,  Chang-Hung Chen ,  Po-Yu Yang ,  Mei-Ying Fan ,  Mu-Kai Tsai ,  Guan-Shyan Lin ,  Tsz-Hui Kuo ,  Cheng-Hsiung Chen

IPC: H01L21/8234 ,  H01L27/11 ,  H01L27/088

Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. Agate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

公开(公告)号：US10276446B1

公开(公告)日：2019-04-30

申请号：US15976848

申请日：2018-05-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei-Chi Lee ,  Han-Tsun Wang ,  Chang-Hung Chen ,  Po-Yu Yang ,  Mei-Ying Fan ,  Mu-Kai Tsai ,  Guan-Shyan Lin ,  Tsz-Hui Kuo ,  Cheng-Hsiung Chen

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11

Abstract: An inverter structure includes a first fin structure and a second fin structure respectively disposed within a P-type transistor region and an N-type transistor region on a substrate. A gate line is disposed on the substrate. A first end of the gate line is within the P-type transistor region, and a second end of the gate line is within the N-type transistor region. Two dummy gate lines are disposed at two sides of the gate line. Each dummy gate line has a third end within the P-type transistor region, and a fourth end within the N-type transistor region. A distance between the first end and the first fin structure is greater than a distance between the third end and the first fin structure. The distance between the second end and the second fin structure is smaller than a distance between the fourth end and the second fin structure.

公开(公告)号：US20180182860A1

公开(公告)日：2018-06-28

申请号：US15391822

申请日：2016-12-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kung-Hong Lee ,  Mu-Kai Tsai ,  Chung-Hsing Lin

IPC: H01L29/51 ,  H01L49/02 ,  H01L27/088 ,  H01L27/092 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor device preferably includes: a first metal-oxide semiconductor (MOS) transistor on a substrate; a first ferroelectric (FE) layer connected to the first MOS transistor; a second MOS transistor on the substrate; and a second FE layer connected to the second MOS transistor. Preferably, the first FE layer and the second FE layer include different capacitance.