公开(公告)号：US11664432B2

公开(公告)日：2023-05-30

申请号：US16556796

申请日：2019-08-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Dirk Utess ,  Zhixing Zhao ,  Dominik M. Kleimaier ,  Irfan A. Saadat ,  Florent Ravaux

IPC: H01L27/092 ,  H01L29/417 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L27/092 ,  H01L29/401 ,  H01L29/7845

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a layout optimization for radio frequency (RF) device performance and methods of manufacture. The structure includes: a first active device on a substrate; source and drain diffusion regions adjacent to the first active device; and a first contact in electrical contact with the source and drain diffusion regions and which is spaced away from the first active device to optimize a stress component in a channel region of the first active device.

公开(公告)号：US20240170576A1

公开(公告)日：2024-05-23

申请号：US18056754

申请日：2022-11-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhixing Zhao ,  Tom Herrmann ,  Jegadheesan Venkatesan

IPC: H01L29/78 ,  H01L27/12

CPC classification number: H01L29/7838 ,  H01L27/1203 ,  H01L29/7831

Abstract: Embodiments of the disclosure provide a structure with a back-gate having oppositely doped semiconductor regions. The structure may include a transistor over a substrate. The transistor includes a gate structure having a gate length. A back-gate region is within the substrate below the gate structure of the transistor. The back-gate region includes a pair of doped semiconductor regions with a P-N junction therebetween. Each of the pair of semiconductor materials has a length extending substantially in parallel with respect to the gate length.

公开(公告)号：US11837605B2

公开(公告)日：2023-12-05

申请号：US17644858

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tom Herrmann ,  Zhixing Zhao ,  Alban Zaka ,  Yiching Chen

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/0653 ,  H01L29/7838

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.

公开(公告)号：US20230290829A1

公开(公告)日：2023-09-14

申请号：US17804201

申请日：2022-05-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Alexander M. Derrickson ,  Ketankumar Harishbhai Tailor ,  Zhixing Zhao ,  Judson R. Holt

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/1004 ,  H01L29/66234 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

公开(公告)号：US20240284680A1

公开(公告)日：2024-08-22

申请号：US18172027

申请日：2023-02-21

Applicant: GlobalFoundries U.S. Inc.

Inventor： Zhixing Zhao ,  Dominik M. Kleimaier ,  Stefan Duenkel

IPC: H10B51/30 ,  G11C11/22 ,  H01L29/78

CPC classification number: H10B51/30 ,  G11C11/2275 ,  H01L29/78391

Abstract: A ferroelectric memory device includes a substrate including a source region and a drain region, and a gate structure disposed over the substrate. The gate structure includes a gate electrode including a plurality of electrode portions arranged in a first direction parallel to a top surface of the substrate, an oxide layer including a plurality of oxide portions corresponding respectively to the plurality of electrode portions, and a ferroelectric layer disposed between the gate electrode and the oxide layer along a second direction perpendicular to the first direction and including a plurality of ferroelectric portions corresponding respectively to the plurality of oxide portions. A least one of the plurality of oxide portions and at least one of the plurality of ferroelectric portions have different thicknesses along the second direction.

公开(公告)号：US12046670B2

公开(公告)日：2024-07-23

申请号：US17488235

申请日：2021-09-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhixing Zhao ,  Manjunatha Prabhu ,  Shafiullah Syed

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/78 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/41783

Abstract: A semiconductor device comprising an active region, and a gate having side portions and a middle portion, whereby the middle portion is arranged between the side portions. The side portions and the middle portion of the gate may be arranged over the active region. The middle portion may be horizontally wider than the side portions. A first gate contact may be arranged over the middle portion.

公开(公告)号：US20230131403A1

公开(公告)日：2023-04-27

申请号：US17452175

申请日：2021-10-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： David C. Pritchard ,  Hongru Ren ,  Zhixing Zhao

IPC: H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L29/40

Abstract: Embodiments of the disclosure provide an integrated circuit (IC) structure including a gate structure over a semiconductor layer. The gate structure includes a first portion having a first horizontal width, and a second portion laterally adjacent the first portion and having a second horizontal width less than the first horizontal width. A gate contact is on the first portion of the gate structure and is not on the second portion of the gate structure.

公开(公告)号：US11916109B2

公开(公告)日：2024-02-27

申请号：US17804201

申请日：2022-05-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Alexander M. Derrickson ,  Ketankumar Harishbhai Tailor ,  Zhixing Zhao ,  Judson R. Holt

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/1004 ,  H01L29/66234 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

公开(公告)号：US20240055434A1

公开(公告)日：2024-02-15

申请号：US18493081

申请日：2023-10-24

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tom Herrmann ,  Zhixing Zhao ,  Alban Zaka ,  Yiching Chen

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/7838 ,  H01L29/0653

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate including a semiconductor-on-insulator (SOI) layer over a buried insulator layer over a base semiconductor layer. The structure further includes a first field effect transistor (FET) adjacent to a second FET, the first FET having a gate electrode on the buried insulator layer and a source and a drain in the base semiconductor layer under the buried insulator layer. The second FET has a source and a drain over the buried insulator layer. The structure further includes a trench isolation in each of the source and the drain of the first FET, the source of the first FET surrounding the trench isolation therein and the drain of the first FET surrounding the trench isolation therein.

公开(公告)号：US20230197731A1

公开(公告)日：2023-06-22

申请号：US17644858

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tom Herrmann ,  Zhixing Zhao ,  Alban Zaka ,  Yiching Chen

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L29/0653 ,  H01L29/7838 ,  H01L21/84

Abstract: A structure including a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes an SOI layer over a buried insulator layer over a base semiconductor layer. The structure includes a high-voltage first field effect transistor (FET) adjacent to a high performance, low voltage second FET. The high voltage FET has a gate electrode on the buried insulator layer, and a source and a drain in the base semiconductor layer under the buried insulator layer. Hence, the buried insulator layer operates as a gate dielectric for the high voltage FET. The low voltage FET has a source and a drain over the buried insulator layer, i.e., in the SOI layer. A trench isolation is in each of the source and the drain of the first, high voltage FET. The source of the high voltage FET surrounds the trench isolation therein.