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    FABRICATING AN ELECTROCONDUCTIVE CONTACT ON A TOP SURFACE OF A TUNNELING MAGNETORESISTANCE ELEMENT
    2.
    发明公开
    FABRICATING AN ELECTROCONDUCTIVE CONTACT ON A TOP SURFACE OF A TUNNELING MAGNETORESISTANCE ELEMENT 审中-公开

    公开(公告)号：US20230413679A1

    公开(公告)日：2023-12-21

    申请号：US17804680

    申请日：2022-05-31

    Applicant: Allegro MicroSystems, LLC

    Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Yen Ting Liu ,  Paolo Campiglio

    IPC: H01L43/12

    CPC classification number: H01L43/12

    Abstract: In one aspect, a method includes depositing a capping layer on a semiconductor device structure. The semiconductor device includes a plurality of tunneling magnetoresistance (TMR) elements, a corresponding one hard mask on each TMR element, a metal layer, and a plurality of electroconductive vias directing connecting the TMR elements to the metal layer. The method further includes depositing an insulator on the capping layer, depositing a first photoresist on the insulator, patterning the first photoresist using photolithography to expose portions of the insulator, etching the exposed portions of the insulator and the hard masks to expose top surfaces of the TMR elements, stripping the first photoresist, and depositing a conducting material on the top surfaces of the TMR elements to form an electroconductive contact.

    Magnetoresistance structure including two hard masks
    4.
    发明授权
    Magnetoresistance structure including two hard masks 有权

    公开(公告)号：US11005036B2

    公开(公告)日：2021-05-11

    申请号：US16732679

    申请日：2020-01-02

    Applicant: Allegro MicroSystems, LLC

    Inventor： Yen Ting Liu ,  Maxim Klebanov ,  Paolo Campiglio ,  Sundar Chetlur

    IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08

    Abstract: A magnetoresistance structure includes a base that includes a conductive layer and a first active element on and in direct contact with the conductive layer. The magnetoresistance structure also includes a pillar structure connected to the base. The pillar structure includes a first hard mask, a capping material, a second active element and a tunnel layer. The magnetoresistance structure also further includes an etching barrier deposited on the pillar and the base; a second hard mask deposited on the etching barrier; and a capping barrier deposited on the second hard mask and covering side walls of the base.

    PATTERNING OF A MAGNETORESISTANCE STRUCTURE INCLUDING TWO HARD MASKS
    5.
    发明申请
    PATTERNING OF A MAGNETORESISTANCE STRUCTURE INCLUDING TWO HARD MASKS 审中-公开

    公开(公告)号：US20200075846A1

    公开(公告)日：2020-03-05

    申请号：US16122019

    申请日：2018-09-05

    Applicant: Allegro MicroSystems, LLC

    Inventor： Yen Ting Liu ,  Maxim Klebanov ,  Paolo Campiglio ,  Sundar Chetlur

    IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10

    Abstract: A method includes depositing on a substrate a magnetoresistance stack, depositing a first hard mask on the magnetoresistance stack, depositing a first photoresist on the first hard mask, patterning the first photoresist to expose portions of the first hard mask, and etching the exposed portions of the first hard mask to expose a portion of the magnetoresistance stack. The method further includes stripping the first photoresist, etching the exposed portions of the magnetoresistance stack and the first hard mask to form a first intermediate structure having a base and a pillar structure, depositing an etch barrier on the first intermediate structure, and depositing a second hard mask on the etch barrier. A second photoresist is deposited on the second hard mask. The method further includes patterning the second photoresist to expose portions of the second hard mask, etching the exposed portions of the second hard mask, stripping the second photoresist, etching a portion of the second hard mask, a portion of the etch barrier and the base to form a second intermediate structure, and depositing a capping barrier on the second intermediate structure.

    MULTI-TERMINAL DEVICES USING MAGNETORESISTANCE ELEMENTS
    7.
    发明公开
    MULTI-TERMINAL DEVICES USING MAGNETORESISTANCE ELEMENTS 审中-公开

    公开(公告)号：US20240085463A1

    公开(公告)日：2024-03-14

    申请号：US17931197

    申请日：2022-09-12

    Applicant: Allegro MicroSystems, LLC

    Inventor： Samridh Jaiswal ,  Paolo Campiglio ,  Sundar Chetlur ,  Maxim Klebanov ,  Yen Ting Liu

    IPC: G01R15/20 ,  G01R19/00

    CPC classification number: G01R15/205 ,  G01R19/0092

    Abstract: In one aspect, a sensor includes a first metal layer portion and a second metal layer portion separated by an insulator material; a conductive material layer in electrical contact with the first metal layer portion and the second metal layer portion; and a tunnel magnetoresistance (TMR) element positioned on and in electrical contact with the conductive material layer. A first current is configured to flow from the first metal layer portion, through the conductive material layer, to the second metal layer portion, and a second current is configured to flow from the first metal layer portion, through the conductive material layer, through the TMR element, and exiting through a top of the TMR element.

    DUAL CIRCUIT DIGITAL ISOLATOR
    10.
    发明申请
    DUAL CIRCUIT DIGITAL ISOLATOR 有权

    公开(公告)号：US20230084169A1

    公开(公告)日：2023-03-16

    申请号：US18051151

    申请日：2022-10-31

    Applicant: Allegro MicroSystems, LLC

    Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

    IPC: H01L23/522 ,  H01L21/8234

    Abstract: An apparatus including; a substrate; an isolator that is formed over the substrate, the isolator including a silicon shield layer that is formed between a first buried oxide (BOX) layer and a second BOX layer; a silicon layer having an oxide trench structure formed therein, the oxide trench structure being arranged to define a first silicon island and a second silicon island; a first electronic circuit that is formed over the first silicon island; and a second electronic circuit that is formed over the second silicon island, the first electronic circuit being electrically coupled to the first electronic circuit.

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