公开(公告)号：US20230413679A1

公开(公告)日：2023-12-21

申请号：US17804680

申请日：2022-05-31

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Yen Ting Liu ,  Paolo Campiglio

IPC: H01L43/12

CPC classification number: H01L43/12

Abstract: In one aspect, a method includes depositing a capping layer on a semiconductor device structure. The semiconductor device includes a plurality of tunneling magnetoresistance (TMR) elements, a corresponding one hard mask on each TMR element, a metal layer, and a plurality of electroconductive vias directing connecting the TMR elements to the metal layer. The method further includes depositing an insulator on the capping layer, depositing a first photoresist on the insulator, patterning the first photoresist using photolithography to expose portions of the insulator, etching the exposed portions of the insulator and the hard masks to expose top surfaces of the TMR elements, stripping the first photoresist, and depositing a conducting material on the top surfaces of the TMR elements to form an electroconductive contact.

公开(公告)号：US11005036B2

公开(公告)日：2021-05-11

申请号：US16732679

申请日：2020-01-02

Applicant: Allegro MicroSystems, LLC

Inventor： Yen Ting Liu ,  Maxim Klebanov ,  Paolo Campiglio ,  Sundar Chetlur

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L43/08

Abstract: A magnetoresistance structure includes a base that includes a conductive layer and a first active element on and in direct contact with the conductive layer. The magnetoresistance structure also includes a pillar structure connected to the base. The pillar structure includes a first hard mask, a capping material, a second active element and a tunnel layer. The magnetoresistance structure also further includes an etching barrier deposited on the pillar and the base; a second hard mask deposited on the etching barrier; and a capping barrier deposited on the second hard mask and covering side walls of the base.

公开(公告)号：US10649481B2

公开(公告)日：2020-05-12

申请号：US16259087

申请日：2019-01-28

Applicant: Allegro MicroSystems, LLC

Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

IPC: G05F3/02 ,  H01L43/02 ,  H03K19/003 ,  H01L27/02

Abstract: An electronic circuit includes a driver circuit having an output terminal that can be coupled to a load to drive the load. A control circuit is coupled to the driver circuit for controlling the driver circuit. A transistor is coupled in series between the driver circuit and the output terminal. The transistor has a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the transistor and configured to provide a constant voltage to the gate terminal to bias the transistor to a conducting state to reduce the susceptibility of the electronic circuit to electromagnetic interference. The biasing circuit includes a voltage regulator, a Zener diode, and a capacitor. The Zener diode and capacitor are coupled to the gate terminal and a reference terminal.

公开(公告)号：US20200075846A1

公开(公告)日：2020-03-05

申请号：US16122019

申请日：2018-09-05

Applicant: Allegro MicroSystems, LLC

Inventor： Yen Ting Liu ,  Maxim Klebanov ,  Paolo Campiglio ,  Sundar Chetlur

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10

Abstract: A method includes depositing on a substrate a magnetoresistance stack, depositing a first hard mask on the magnetoresistance stack, depositing a first photoresist on the first hard mask, patterning the first photoresist to expose portions of the first hard mask, and etching the exposed portions of the first hard mask to expose a portion of the magnetoresistance stack. The method further includes stripping the first photoresist, etching the exposed portions of the magnetoresistance stack and the first hard mask to form a first intermediate structure having a base and a pillar structure, depositing an etch barrier on the first intermediate structure, and depositing a second hard mask on the etch barrier. A second photoresist is deposited on the second hard mask. The method further includes patterning the second photoresist to expose portions of the second hard mask, etching the exposed portions of the second hard mask, stripping the second photoresist, etching a portion of the second hard mask, a portion of the etch barrier and the base to form a second intermediate structure, and depositing a capping barrier on the second intermediate structure.

公开(公告)号：US10234887B2

公开(公告)日：2019-03-19

申请号：US15161529

申请日：2016-05-23

Applicant: Allegro Microsystems, LLC

Inventor： Richard B. Cooper ,  Maxim Klebanov ,  Washington Lamar ,  Devon Fernandez

IPC: G06F3/02 ,  G05F3/02 ,  H01L43/02 ,  H03K19/003 ,  H01L27/02

Abstract: An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.

公开(公告)号：US20180337168A1

公开(公告)日：2018-11-22

申请号：US15601141

申请日：2017-05-22

Applicant: Allegro Microsystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar

IPC: H01L27/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/87 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L27/0255 ,  H01L21/26513 ,  H01L21/76202 ,  H01L21/76224 ,  H01L27/0259 ,  H01L27/092 ,  H01L27/22 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/417 ,  H01L29/7801 ,  H01L29/87

Abstract: A gate-less electrostatic discharge (ESD) protection device is provided that can be formed in various complementary metal-oxide-semiconductor (CMOS) systems. The gate-less ESD event protection device includes a substrate, a first doped region formed in the substrate, a second doped region extending into the first doped region, a third doped region extending into the first doped region, a first node formed over a portion of the second doped region and coupled to a source terminal and a second node formed over the third doped region and coupled to a drain terminal. The gate-less ESD protection devices can be formed such that no gate electrode is formed and the gate-less ESD protection device does not include a gate terminal. Thus, an operating voltage range of the gate-less ESD protection device is not limited by gate oxide degradation.

公开(公告)号：US20180061820A1

公开(公告)日：2018-03-01

申请号：US15245689

申请日：2016-08-24

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar ,  William P. Taylor

IPC: H01L27/02 ,  H01L43/02 ,  H01L43/12 ,  G01R33/00

CPC classification number: G01R33/0076 ,  H01L23/60 ,  H01L43/02 ,  H01L43/12

Abstract: An apparatus includes a package, a plurality of external connections extending outside the package, and a first die having a first electrical contact coupled to a first connection of the plurality of external connections. The apparatus also includes a second die having a second electrical contact coupled to a second connection of the plurality of external connections. A conductor is electrically coupled between the first contact and the second contact to allow electrostatic discharge current to flow between the first die to the second die.

公开(公告)号：US09866014B2

公开(公告)日：2018-01-09

申请号：US14619626

申请日：2015-02-11

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Washington Lamar

IPC: H02H9/04

CPC classification number: H02H9/04

Abstract: In an embodiment, an electronic device comprises a shared electrical over-stress (EOS) protection circuit. The shared EOS protection circuit may be coupled between a power input terminal and ground terminal to provide an EOS current path from the power input terminal to the ground terminal, and coupled between the output terminal and the ground terminal to provide an EOS current path from the output terminal to the ground terminal. The electronic device may also include a power interruption mitigation circuit to provide power to the electronic device during interruptions or fluctuations in external power.

公开(公告)号：US20170250143A1

公开(公告)日：2017-08-31

申请号：US15053397

申请日：2016-02-25

Applicant: Allegro Microsystems, LLC

Inventor： William Wilkinson ,  Washington Lamar ,  Maxim Klebanov

IPC: H01L23/60 ,  H01L23/31 ,  H01L43/02 ,  H01L25/065

CPC classification number: H01L23/60 ,  H01L23/3142 ,  H01L23/495 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L43/02 ,  H01L2224/04042 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: An integrated circuit device includes a package and at least two leads exposed external to the package to permit electrical connections to the package. A first die situated in the package has a first substrate and at least a first terminal electrically coupled to a first one of the leads. A second die situated in the package has a second substrate and at least a second terminal electrically coupled to a second one of the lead. An adhesive material holding the first and second die in place forms a voltage-triggered conduction path between the first and second die electrically that isolates the second die from the first die under a first condition and provides an ESD current path between the first one of the leads and the second one of the leads under a second condition.

公开(公告)号：US20240085463A1

公开(公告)日：2024-03-14

申请号：US17931197

申请日：2022-09-12

Applicant: Allegro MicroSystems, LLC

Inventor： Samridh Jaiswal ,  Paolo Campiglio ,  Sundar Chetlur ,  Maxim Klebanov ,  Yen Ting Liu

IPC: G01R15/20 ,  G01R19/00

CPC classification number: G01R15/205 ,  G01R19/0092

Abstract: In one aspect, a sensor includes a first metal layer portion and a second metal layer portion separated by an insulator material; a conductive material layer in electrical contact with the first metal layer portion and the second metal layer portion; and a tunnel magnetoresistance (TMR) element positioned on and in electrical contact with the conductive material layer. A first current is configured to flow from the first metal layer portion, through the conductive material layer, to the second metal layer portion, and a second current is configured to flow from the first metal layer portion, through the conductive material layer, through the TMR element, and exiting through a top of the TMR element.