BACKSIDE CONTACTS FOR STACKED FIELD EFFECT TRANSISTORS
摘要:
Embodiments are disclosed for a semiconductor device and a method for fabrication. The device includes a first gate, having a top FET that is disposed above a bottom FET, and in electrical contact with a top source/drain epitaxial (S/D epi) and a back end of line (BEOL) interconnect. Additionally, the device includes the bottom FET. The bottom FET is in electrical contact with a bottom S/D epi. Further, a shallow backside contact is in electrical contact with the bottom S/D epi. Additionally, the device includes a deep via that is in electrical contact with the BEOL interconnect and the shallow backside contact. The deep via and the shallow backside contact provide a conductive path between the BEOL interconnect and the bottom S/D epi.
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