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    Electronic devices having spiral conductive structures
    1.
    发明授权
    Electronic devices having spiral conductive structures 有权

    公开(公告)号：US10784333B2

    公开(公告)日：2020-09-22

    申请号：US16456610

    申请日：2019-06-28

    申请人： International Business Machines Corporation

    发明人： Peng Xu ,  Kangguo Cheng ,  Xuefeng Liu ,  Chi-Chun Liu ,  Yongan Xu

    IPC分类号： H01L49/02 ,  H01L21/3105 ,  H01L23/522

    摘要： Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

    Integrating metal-insulator-metal capacitors with fabrication of vertical field effect transistors
    2.
    发明授权
    Integrating metal-insulator-metal capacitors with fabrication of vertical field effect transistors 有权

    公开(公告)号：US10699959B2

    公开(公告)日：2020-06-30

    申请号：US16396198

    申请日：2019-04-26

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Xuefeng Liu ,  Heng Wu ,  Peng Xu

    IPC分类号： H01L21/8234 ,  H01L49/02 ,  H01L27/06 ,  H01L29/78 ,  H01L29/66 ,  H01L21/822

    摘要： Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

    ELECTRONIC DEVICES HAVING SPIRAL CONDUCTIVE STRUCTURES
    3.
    发明申请
    ELECTRONIC DEVICES HAVING SPIRAL CONDUCTIVE STRUCTURES 审中-公开

    公开(公告)号：US20190341444A1

    公开(公告)日：2019-11-07

    申请号：US16456610

    申请日：2019-06-28

    申请人： International Business Machines Corporation

    发明人： Peng Xu ,  Kangguo Cheng ,  Xuefeng Liu ,  Chi-Chun Liu ,  Yongan Xu

    IPC分类号： H01L49/02 ,  H01L21/3105

    摘要： Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

    INTEGRATING METAL-INSULATOR-METAL CAPACITORS WITH FABRICATION OF VERTICAL FIELD EFFECT TRANSISTORS
    4.
    发明申请
    INTEGRATING METAL-INSULATOR-METAL CAPACITORS WITH FABRICATION OF VERTICAL FIELD EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20190259666A1

    公开(公告)日：2019-08-22

    申请号：US16396013

    申请日：2019-04-26

    申请人： International Business Machines Corporation

    发明人： Kangguo Cheng ,  Xuefeng Liu ,  Heng Wu ,  Peng Xu

    IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/822 ,  H01L29/78 ,  H01L27/06 ,  H01L49/02

    摘要： Device and methods are provided for fabricating semiconductor devices in which metal-insulator-metal (MIM) capacitor devices are integrally formed with vertical field effect transistor (FET) devices. For example, a semiconductor device includes first and second vertical FET devices, and a capacitor device, formed in different device regions of a substrate. A gate electrode of the first FET device and a first capacitor electrode of the capacitor device are patterned from a same first layer of conductive material. A gate electrode of the second FET device and a second capacitor electrode of the capacitor device are patterned from a same second layer of conductive material. A gate dielectric layer of the second FET device and a capacitor insulator layer of the capacitor device are formed from a same layer of dielectric material.

    On chip bias temperature instability characterization of a semiconductor device
    7.
    发明授权
    On chip bias temperature instability characterization of a semiconductor device 有权
    半导体器件的片上偏置温度不稳定性表征

    公开(公告)号：US09404960B2

    公开(公告)日：2016-08-02

    申请号：US14041422

    申请日：2013-09-30

    申请人： International Business Machines Corporation

    发明人： Hanyi Ding ,  Xuefeng Liu ,  Alvin W. Strong ,  Randy L. Wolf

    IPC分类号： G01R31/26 ,  G01R31/28

    CPC分类号： G01R31/2628 ,  G01R31/2623 ,  G01R31/2822

    摘要： Embodiments of the present invention provide a circuit and method to characterize the impact of bias temperature instability on semiconductor devices. The circuit comprises a transistor having a gate, drain, source, and body terminal. Two AC pad sets each having a plurality of conductive pads. Two DC pads are in communication with a DC supply and/or meter. The gate terminal is in communication with a first conductive pad included in the plurality of conductive pads of each of the AC pad sets. The drain terminal is in communication with a second conductive pad of an AC pad set and the source terminal with a second conductive pad of another AC pad set. One DC pad is in communication with the gate terminal through a first serial resistor and another DC pad with the body terminal through a second serial resistor and provides an open-circuit for the gate and body terminals.

    摘要翻译： 本发明的实施例提供了表征偏压温度不稳定性对半导体器件的影响的电路和方法。 电路包括具有栅，漏，源和体端子的晶体管。 两个AC焊盘组均具有多个导电焊盘。 两个直流焊盘与直流电源和/或电表通讯。 栅极端子与包括在每个AC焊盘组的多个导电焊盘中的第一导电焊盘连通。 漏极端子与AC焊盘组的第二导电焊盘和源极端子与另一个AC焊盘组的第二导电焊盘连通。 一个直流焊盘通过第一串联电阻器与栅极端子连通，另一个直流焊盘通过第二串联电阻器与主体端子连接，并为栅极和主体端子提供开路。

    Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs
    9.
    发明授权
    Two step fin etch and reveal for VTFETs and high breakdown LDVTFETs 有权

    公开(公告)号：US10811528B2

    公开(公告)日：2020-10-20

    申请号：US15927962

    申请日：2018-03-21

    申请人： International Business Machines Corporation

    发明人： Mona Ebrish ,  Xuefeng Liu ,  Brent Anderson ,  Huiming Bu ,  Junli Wang

    IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/66

    摘要： High breakdown voltage devices are provided. In one aspect, a method of forming a device having a VTFET and a LDVTFET includes: forming a LDD in an LDVTFET region; patterning fin(s) in a VTFET region to a depth D1; patterning fin(s) in the LDVTFET region, through the LDD, to a depth D2>D1; forming bottom source/drains at a base of the VTFET/LDVTFET fins; burying the VTFET/LDVTFET fins in a gap fill dielectric; recessing the gap fill dielectric to full expose the VTFET fin(s) and partially expose the LDVTFET fin(s); forming bottom spacers directly on the bottom source/drains in the VTFET region and directly on the gap fill dielectric in the LDVTFET region; forming gates alongside the VTFET/LDVTFET fins; forming top spacers above the gates; and forming top source/drains above the top spacers. A one-step fin etch and devices having VTFET and long channel VTFETs are also provided.