公开(公告)号：US20220093459A1

公开(公告)日：2022-03-24

申请号：US17027897

申请日：2020-09-22

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Yongan Xu ,  Hsueh-Chung Chen

IPC: H01L21/768 ,  H01L21/3213

Abstract: A method of forming a BEOL interconnect structure having improved resistance-capacitance is provided in which a via metal layer is created by a first metallization process and thereafter shrunk by a subtractive etch; these steps relax the critical dimension, ensure a via straight profile, avoid via chamfering and bowing, and maximize metal volume. Top trench metallization is then performed above the via metal layer; this step eliminates reactive ion etch lag and ensures no metallization void issues.

公开(公告)号：US11171001B2

公开(公告)日：2021-11-09

申请号：US16669861

申请日：2019-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Lawrence A. Clevenger ,  Yann Mignot ,  Cornelius Brown Peethala

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105 ,  G03F7/00 ,  G03F7/16 ,  G03F7/20 ,  G03F7/09

Abstract: A semiconductor device includes at least one mandrel including a dielectric material, and at least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material.

公开(公告)号：US11131919B2

公开(公告)日：2021-09-28

申请号：US16015994

申请日：2018-06-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yongan Xu ,  Zhenxing Bi ,  Yann Mignot ,  Nelson Felix ,  Ekmini A. De Silva

IPC: G03F7/11 ,  G03F7/42 ,  G03F7/20 ,  G03F7/36 ,  G03F7/09 ,  G03F1/22

Abstract: A method of removing layers of an extreme ultraviolet (EUV) pattern stack is provided. The method includes forming one or more resist templates on an upper hardmask layer. The method further includes exposing portions of the surface of the upper hardmask layer to a dry etch process to produce modified and activated surfaces. The method further includes etching the modified and activated surfaces to expose an underlying organic planarization layer.

公开(公告)号：US11069564B2

公开(公告)日：2021-07-20

申请号：US16378608

申请日：2019-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Yann Mignot ,  James Kelly ,  Lawrence A. Clevenger

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/3213

Abstract: A technique relates to a semiconductor device. Mandrels are formed on a substrate, the mandrels including a first metal layer. A second metal layer is formed on the substrate adjacent to the first metal layer, the first and second metal layers being separated by spacer material.

公开(公告)号：US11031246B2

公开(公告)日：2021-06-08

申请号：US16801644

申请日：2020-02-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Yann Mignot ,  Yongan Xu ,  Oleg Gluschenkov

IPC: H01L21/033 ,  H01L21/3115 ,  G03F7/20 ,  H01L21/311 ,  H01L21/308

Abstract: A method is presented for amplifying extreme ultraviolet (EUV) lithography pattern transfer into a hardmask and preventing hard mask micro bridging effects due to resist residue in a semiconductor structure. The method includes forming a top hardmask over an organic planarization layer (OPL), depositing a photoresist over the top hardmask, patterning the photoresist using EUV lithography, performing ion implantation to create doped regions within the exposed top hardmask and regions of hardmask underneath resist residue, stripping the photoresist, and selectively etching the top hardmask by either employing positive tone or negative tone etch based on an implantation material.

公开(公告)号：US10784333B2

公开(公告)日：2020-09-22

申请号：US16456610

申请日：2019-06-28

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Xuefeng Liu ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L49/02 ,  H01L21/3105 ,  H01L23/522

Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

公开(公告)号：US10672705B2

公开(公告)日：2020-06-02

申请号：US16671445

申请日：2019-11-01

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Junli Wang ,  Yann Mignot ,  Joe Lee

IPC: H01L23/48 ,  H01L23/522 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/768 ,  H01L21/3105

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.

公开(公告)号：US20200098581A1

公开(公告)日：2020-03-26

申请号：US16666948

申请日：2019-10-29

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Ekmini Anuja De Silva ,  Su Chen Fan ,  Yann Mignot

IPC: H01L21/308 ,  G03F1/22 ,  H01L21/033

Abstract: Semiconductor structures fabricated via extreme ultraviolet (EUV) lithographic patterning techniques implementing directional deposition on a EUV resist mask improves selectivity and critical dimension control during the patterning of features in multiple layers of the semiconductor substrate. A semiconductor structure includes a substrate structure having an extreme ultraviolet resist mask disposed over one or more additional layers of the substrate structure. The extreme ultraviolet resist mask defines patterning features. A hard mask layer including a hard mask material is disposed on the extreme ultraviolet resist mask and covers the patterning features of the extreme ultraviolet resist mask.

公开(公告)号：US20200098578A1

公开(公告)日：2020-03-26

申请号：US16139819

申请日：2018-09-24

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Ekmini Anuja De Silva ,  Su Chen Fan ,  Yann Mignot

IPC: H01L21/308 ,  H01L21/033 ,  G03F1/22

Abstract: Extreme ultraviolet (EUV) lithographic patterning methods are provided which implement directional deposition on the EUV resist mask to improve selectivity and critical dimension control during the patterning of features in multiple layers. A hard mask material is deposited on a substrate structure using directional deposition. The hard mask material forms a hard mask layer that covers patterning features of an EUV resist mask of the substrate structure. The hard mask material is etched selective to a layer underlying the EUV resist mask to remove portions of the hard mask material that were deposited on the underlying layer during the directional deposition without uncovering the patterning features of the EUV resist mask. At least one layer of the substrate structure is patterned based on the EUV resist mask and the hard mask layer.

公开(公告)号：US20200066632A1

公开(公告)日：2020-02-27

申请号：US16671445

申请日：2019-11-01

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Junli Wang ,  Yann Mignot ,  Joe Lee

IPC: H01L23/522 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/768 ,  H01L21/3105

Abstract: A method for manufacturing a semiconductor device includes forming a first interconnect level having a conductive metal layer formed in a first dielectric layer. In the method, a cap layer is formed on the first interconnect level, and a second interconnect level including a second dielectric layer is formed on the cap layer. The method also includes forming a third interconnect level including a third dielectric layer on the second interconnect level. An opening is formed through the second and third interconnect levels and over the conductive metal layer. Sides of the opening are lined with a spacer material, and a portion of the cap layer at a bottom of the opening is removed from a top surface of the conductive metal layer. The spacer material is removed from the opening, and a conductive material layer is deposited in the opening on the conductive metal layer.