公开(公告)号：US11182722B2

公开(公告)日：2021-11-23

申请号：US16361530

申请日：2019-03-22

Applicant: International Business Machines Corporation

Inventor： Alex Richard Hubbard ,  Spyridon Skordas ,  Marc A. Bergendahl ,  Cody John Murray ,  Gauri Karve ,  Lawrence A. Clevenger

IPC: G06Q10/06 ,  G05B15/02 ,  G06N20/20

Abstract: A method includes monitoring with at least one monitoring tool one or more activities associated with an enterprise. The method further includes analyzing data input from the at least one monitoring tool of the one or more activities, and determining, based on analytics performed on the data input and an implemented policy, when the one or more activities qualifies as an incident. A remedial response responsive to the incident is initiated. The monitoring, analyzing, determining and initiating steps are performed by at least one processing device including a processor operatively coupled to a memory.

公开(公告)号：US20210320190A1

公开(公告)日：2021-10-14

申请号：US16848451

申请日：2020-04-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Eric Miller ,  Fee Li Lie ,  Gauri Karve ,  Marc A. Bergendahl ,  John Ryan Sporre

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H04L9/32 ,  B82Y10/00 ,  H02M3/155

Abstract: Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip includes a substrate. The semiconductor chip includes multiple devices formed on the substrate. Each device includes multiple fins. A gate is formed on the multiple fins with a gate cut (CT) design that results in random distribution of complete gate cut and incomplete gate cut for each of the multiple devices based on a natural process variation in semiconductor manufacturing for each device. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

公开(公告)号：US20210320070A1

公开(公告)日：2021-10-14

申请号：US16844608

申请日：2020-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Eric Miller ,  Fee Li Lie ,  Gauri Karve ,  Marc A. Bergendahl ,  John Sporre

IPC: H01L23/544 ,  H01L27/088 ,  H01L21/8234 ,  G06F21/75

Abstract: Methods, and devices related to authentication of chips using physical unclonable function (PUF) are disclosed. The semiconductor chip has a substrate having a major surface. The semiconductor chip has a boundary defined on the major surface in accordance with a ground rule associated with a gate cut passing (CT) fin formed on the major surface. The semiconductor chip has multiple non-planar devices fabricated on the surface at the boundary. The CT fin forms a random distribution of field effect transistors (FETs) with varying work function metal (WFM) thickness that includes some FETs that fail the ground rule and other FETs that meet the ground rule. A physical unclonable function (PUF) region is defined in accordance with the random distribution.

公开(公告)号：US11043494B2

公开(公告)日：2021-06-22

申请号：US16460018

申请日：2019-07-02

Applicant: International Business Machines Corporation

Inventor： Lawrence A. Clevenger ,  Leigh Anne H. Clevenger ,  Mona A. Ebrish ,  Gauri Karve ,  Fee Li Lie ,  Deepika Priyadarshini ,  Indira Priyavarshini Seshadri ,  Nicole A. Saulnier

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/161 ,  H01L29/78 ,  H01L21/308 ,  H01L21/762 ,  H01L29/10

Abstract: A method for fabricating fin field effect transistors comprises creating a pattern of self-aligned small cavities for P-type material growth using at least two hard mask layers, generating a pre-defined isolation area around each small cavity using a vertical spacer, selectively removing N-type material from the self-aligned small cavities, and growing P-type material in the small cavities. The P-type material may be silicon germanium (SiGe) and the N-type material may be tensile Silicon (t-Si). The pattern of self-aligned small cavities for P-type material growth is created by depositing two hard mask materials over a starting substrate wafer, selectively depositing photo resist over a plurality N-type areas, reactive ion etching to remove the second hard mask layer material over areas not covered by photo resist to create gaps in second hard mask layer, and removing the photo resist to expose the second hard mask material in the N-type areas.

公开(公告)号：US10964812B2

公开(公告)日：2021-03-30

申请号：US16670534

申请日：2019-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xuefeng Liu ,  Junli Wang ,  Brent A. Anderson ,  Terence B. Hook ,  Gauri Karve

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/10 ,  H01L27/088

Abstract: A method for fabricating a semiconductor device includes forming a vertical field-effect transistor (FET) device including a plurality of first fin structures in a vertical FET device area of a substrate, and forming an input/output (IO) FET device including at least two second fin structures in an IO FET device area of the substrate. The at least two fin structures are connected by a channel having a length determined based on at least one voltage for implementing the IO FET device. Forming the vertical FET and IO FET devices includes selectively exposing a portion of the IO FET device area by selectively removing a portion of a first spacer formed on the substrate in the IO FET device area.

公开(公告)号：US10937810B2

公开(公告)日：2021-03-02

申请号：US16541429

申请日：2019-08-15

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/84 ,  H01L29/78

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

公开(公告)号：US20200279913A1

公开(公告)日：2020-09-03

申请号：US16290165

申请日：2019-03-01

Applicant: International Business Machines Corporation

Inventor： Mona A. Ebrish ,  Fee Li Lie ,  Nicolas Loubet ,  Gauri Karve ,  Indira Seshadri ,  Lawrence A. Clevenger ,  Leigh Anne H. Clevenger

IPC: H01L29/06 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

Abstract: Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.

公开(公告)号：US10727273B2

公开(公告)日：2020-07-28

申请号：US16159798

申请日：2018-10-15

Applicant: International Business Machines Corporation

Inventor： Praveen Joseph ,  Xuefeng Liu ,  Gauri Karve ,  Eric Raymond Evarts

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: A MRAM-TFT unit cell and a method for fabricating the same. The MRAM-TFT unit cell includes a MRAM device and a TFT device electrically coupled to the MRAM device. The MRAM device and the TFT device are situated within a common plane of the MRAM-TFT cell. The method includes forming a TFT device comprising a source/drain region, and a semiconducting layer on a substrate. A magnetic tunnel junction stack (MTJ) is formed in contact with the source region. A first contact is formed on the MTJ, and a second contact is formed on the drain region. A first interconnect metal layer is formed in contact with the first contact, and a second first interconnect metal layer is formed in contact with the second contact. A third contact is formed on a gate region of the TFT device. A third interconnect metal layer is formed in contact with the third contact.

公开(公告)号：US10438972B2

公开(公告)日：2019-10-08

申请号：US15263005

申请日：2016-09-12

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/84

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

公开(公告)号：US20190172940A1

公开(公告)日：2019-06-06

申请号：US16267618

申请日：2019-02-05

Applicant: International Business Machines Corporation

Inventor： Andrew M. Greene ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Eric R. Miller ,  Pietro Montanini

IPC: H01L29/78 ,  H01L29/66

Abstract: FinFET devices comprising multilayer gate spacers are provided, as well as methods for fabricating FinFET devices in which multilayer gate spacers are utilized to prevent or otherwise minimize the erosion of vertical semiconductor fins when forming the gate spacers. For example, a method for fabricating a semiconductor device comprises forming a dummy gate structure over a portion of a vertical semiconductor fin of a FinFET device, and forming a multilayer gate spacer on the dummy gate structure. The multilayer gate spacer comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer has etch selectivity with respect to the vertical semiconductor fin and the second dielectric layer. In one embodiment, the first dielectric layer comprises silicon oxycarbonitride (SiOCN) and the second dielectric layer comprises silicon boron carbon nitride (SiBCN).