公开(公告)号：US20250159997A1

公开(公告)日：2025-05-15

申请号：US18509382

申请日：2023-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Brent A. Anderson ,  Jay William Strane ,  Ruilong Xie ,  Albert M. Chu ,  Junli Wang

IPC: H01L27/12 ,  H01L21/822

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor on a substrate; a second transistor on top of the first transistor; and a source/drain (S/D) contact contacting a first S/D region of the first transistor, where the S/D contact has a horizontal portion and a vertical portion, the horizontal portion extending from a sidewall of the vertical portion and a portion of the horizontal portion being vertically between the first S/D region of the first transistor and a second S/D region of the second transistor. A method of forming the same is also provided.

公开(公告)号：US20250151342A1

公开(公告)日：2025-05-08

申请号：US18502125

申请日：2023-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chen Zhang ,  Ruilong Xie ,  Shay Reboh ,  Junli Wang

IPC: H01L29/06 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes a first group of field-effect-transistors (FETs); a second group of FETs on top of the first group of FETs; a first half-single-diffusion-break (H-SDB) underneath and being separated from one of the FETs of the second group by a middle-dielectric-insulator (MDI) layer; and a second H-SDB on top of and being separated from one of the FETs of the first group by the MDI layer, where the first H-SDB insulates a source/drain (S/D) region of a first FET of the first group of FETs from a S/D region of a second FET of the first group of FETs, and the second H-SDB insulates a S/D region of a first FET of the second group of FETs from a S/D region of a second FET of the second group of FETs. A method of forming the same is also provided.

公开(公告)号：US12268026B2

公开(公告)日：2025-04-01

申请号：US17657006

申请日：2022-03-29

Applicant: International Business Machines Corporation

Inventor： Junli Wang ,  Brent A Anderson ,  Terence Hook ,  Indira Seshadri ,  Albert M. Young ,  Stuart Sieg ,  Su Chen Fan ,  Shogo Mochizuki

IPC: H10D64/23 ,  H10D64/01

Abstract: A high aspect ratio contact structure formed within a dielectric material includes a top portion and a bottom portion. The top portion of the contact structure includes a tapering profile towards the bottom portion. A first metal stack surrounded by an inner spacer is located within the top portion of the contact structure and a second metal stack is located within the bottom portion of the contact structure. A width of the bottom portion of the contact structure is greater than a minimum width of the top portion of the contact structure.

公开(公告)号：US12268016B2

公开(公告)日：2025-04-01

申请号：US17564571

申请日：2021-12-29

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Junli Wang ,  Brent A Anderson ,  Chen Zhang ,  Heng Wu ,  Alexander Reznicek

IPC: H10D30/62 ,  H01L23/522 ,  H01L23/528 ,  H10D64/01

Abstract: A channel fin extends vertically above a bottom source/drain region, a protective liner is positioned along opposite sidewalls of the bottom source/drain region. The bottom source/drain region is positioned above a semiconductor layer in contact with a first portion of an inner spacer. A first metal layer is positioned between the first portion of the inner spacer and a second portion of the inner spacer, the first portion of the inner spacer partially covers a top surface of the first metal layer and the second portion of the inner spacer substantially covers a bottom surface of the first metal layer for providing a buried power rail. A shallow trench isolation region is positioned above an exposed portion of the first metal layer, the shallow trench isolation region is adjacent to the first portion of the inner spacer, the semiconductor layer, and the bottom source/drain region.

公开(公告)号：US20250040199A1

公开(公告)日：2025-01-30

申请号：US18359922

申请日：2023-07-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Brent A. Anderson ,  Albert M. Chu ,  Junli Wang ,  Jay William Strane

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first transistor having a first source/drain (S/D) region; a second transistor having a second S/D region, the second transistor being stacked on top of the first transistor; and a first S/D contact shared by the first S/D region of the first transistor and the second S/D region of the second transistor, where the first S/D contact has a first portion and a second portion, the first portion being in direct contact with a top surface of the first S/D region of the first transistor and in direct contact with a bottom surface of the second S/D region, and the second portion being in direct contact with an inner sidewall of the second S/D region of the second transistor. A method of manufacturing the semiconductor structure is also provided.

公开(公告)号：US20250006786A1

公开(公告)日：2025-01-02

申请号：US18214642

申请日：2023-06-27

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Brent A. Anderson ,  Junli Wang ,  Jay William Strane ,  Albert M. Chu

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device comprises a top field effect transistor (FET) and a bottom FET in a stacked profile. The semiconductor device also comprises a gate. The gate comprises two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises an insulator liner. The insulator liner interfaces with the two top-FET gate extensions and two bottom-FET gate extensions. The semiconductor device also comprises a dielectric that interfaces with the insulator liner.

公开(公告)号：US20250006736A1

公开(公告)日：2025-01-02

申请号：US18214682

申请日：2023-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Biswanath Senapati ,  Shahrukh Khan ,  Utkarsh Bajpai ,  Terence Hook ,  Chen Zhang ,  Junli Wang

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.

公开(公告)号：US20240395816A1

公开(公告)日：2024-11-28

申请号：US18321838

申请日：2023-05-23

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Nicolas Jean Loubet ,  Shogo Mochizuki ,  Junli Wang

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/48 ,  H01L29/04 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78

Abstract: Aspects of the invention are directed to fabrication methods and resulting structures for providing transistors having hybrid crystal orientation channels and mixed crystal orientation bottom epitaxies. In a non-limiting embodiment, a first fin having a first crystal orientation is formed in a first region of a substrate having a second crystal orientation. A second fin having the second crystal orientation is formed in a second region of the substrate. The second fin is formed directly on a surface of the substrate. A mixed crystal bottom source or drain region is formed between the first fin and the first region of the substrate and a single crystal bottom source or drain region having the second crystal orientation is formed on sidewalls of the second fin and on the surface of the substrate in the second region.

公开(公告)号：US12142656B2

公开(公告)日：2024-11-12

申请号：US17541894

申请日：2021-12-03

Applicant: International Business Machines Corporation

Inventor： Albert Chu ,  Junli Wang ,  Albert M. Young ,  Vidhi Zalani ,  Dechao Guo

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/786

Abstract: A semiconductor structure includes a first transistor device comprising a plurality of channel regions. The semiconductor structure further includes a second transistor device comprising a plurality of channel regions. The first transistor device and the second transistor device are disposed in a stacked configuration. The plurality of channel regions of the first transistor device are disposed in a staggered configuration relative to the plurality of channel regions of the second transistor device.

公开(公告)号：US20240194601A1

公开(公告)日：2024-06-13

申请号：US18062624

申请日：2022-12-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Albert M. Young ,  Junli Wang ,  Brent A. Anderson ,  Ruilong Xie ,  Lawrence A. Clevenger ,  REINALDO VEGA

IPC: H01L23/528 ,  G06F30/392 ,  G06F30/394 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L23/5286 ,  G06F30/392 ,  G06F30/394 ,  H01L23/5226 ,  H01L27/0922

Abstract: A semiconductor structure is presented having a plurality of circuit rows, a plurality of first power rails positioned on front sides of the plurality of circuit rows, a plurality of second power rails positioned on back sides of the plurality of circuit rows, and power tap cells associated with each the plurality of circuit rows, wherein each of the power tap cells includes one or more power vias connecting at least one first power rail of the plurality of first power rails to at least one second power rail of the plurality the second power rails. In one instance, the plurality of second power rails are orthogonal to the plurality of first power rails. in another instance, the plurality of first power rails are horizontally offset from the plurality of second power rails. The one or more power vias include at least two or more different sized power vias.