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公开(公告)号:US11605672B2
公开(公告)日:2023-03-14
申请号:US17128786
申请日:2020-12-21
发明人: Julien Frougier , Nicolas Loubet , Ruilong Xie , Daniel Chanemougame , Ali Razavieh , Kangguo Cheng
IPC分类号: H01L27/24 , H01L45/00 , H01L29/78 , H01L21/3213
摘要: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.
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公开(公告)号:US10991808B2
公开(公告)日:2021-04-27
申请号:US16733846
申请日:2020-01-03
发明人: Julien Frougier , Nicolas Loubet , Ruilong Xie , Daniel Chanemougame , Ali Razavieh , Kangguo Cheng
IPC分类号: H01L23/525 , H01L29/43 , H01L29/78 , H01L21/3213 , H01L21/3105 , H01L49/00 , H01L29/417 , H01L29/66 , H04L29/08 , H01L27/24 , H01L27/22
摘要: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
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公开(公告)号:US10566436B2
公开(公告)日:2020-02-18
申请号:US16373242
申请日:2019-04-02
发明人: Julien Frougier , Nicolas Loubet , Ruilong Xie , Daniel Chanemougame , Ali Razavieh , Kangguo Cheng
IPC分类号: H01L29/43 , H01L23/525 , H01L29/78 , H01L21/3213 , H01L21/3105 , H01L49/00 , H04L29/08
摘要: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, a trench contact formed on and in contact with the source/drain, and a source/drain contact formed on an in contact with the trench contact. A recess is formed in a portion of the source/drain contact using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the source/drain contact. A metallization layer is formed in contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.
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公开(公告)号:US09299721B2
公开(公告)日:2016-03-29
申请号:US14280998
申请日:2014-05-19
发明人: Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh , Kejia Wang , Daniel Chanemougame
CPC分类号: H01L27/0886 , H01L21/845 , H01L27/1211 , H01L29/0649 , H01L29/161 , H01L29/66795
摘要: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.
摘要翻译: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物,以及在第二半导体区域上方并邻近间隔物形成第三半导体区域,其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分,从第一半导体区域形成第一组散热片,以及从第二和第三半导体区域形成第二组散热片。
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公开(公告)号:US20190252465A1
公开(公告)日:2019-08-15
申请号:US15894108
申请日:2018-02-12
发明人: Julien Frougier , Nicolas Loubet , Ruilong Xie , Daniel Chanemougame , Ali Razavieh , Kangguo Cheng
CPC分类号: H01L27/2436 , H01L21/32139 , H01L29/785 , H01L45/1683
摘要: Fabricating a steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate disposed upon the fin, a cap disposed on the gate, and a trench extending to the source/drain. A trench contact is formed in the trench in contact with the source/drain. A recess is formed in a portion of the trench contact below a top surface of the cap using a recess patterning process. A bi-stable resistive system (BRS) material is deposited in the recess in contact with the portion of the trench contact. A source/drain contact is formed upon the BRS material, a portion of the trench contact, the BRS material, and a portion of the source/drain contact forming a reversible switch.
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公开(公告)号:US20190109177A1
公开(公告)日:2019-04-11
申请号:US15729758
申请日:2017-10-11
摘要: Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.
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公开(公告)号:US10170520B1
公开(公告)日:2019-01-01
申请号:US15894128
申请日:2018-02-12
发明人: Julien Frougier , Nicolas Loubet , Ruilong Xie , Daniel Chanemougame , Ali Razavieh , Kangguo Cheng
IPC分类号: H01L29/02 , H01L27/24 , H01L29/06 , H01L23/535 , H01L29/78 , H01L45/00 , H01L29/66 , H01L21/768 , H01L21/28
摘要: Fabricating a negative capacitance steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin, a source/drain, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, and an inter-layer dielectric. A source/drain recess is formed in the inter-layer dielectric extending to the trench contact, and a gate recess is formed in the inter-layer dielectric extending to the gate. A ferroelectric material is deposited within the gate recess, and a source/drain contact is formed within the source/drain recess. A gate contact is formed within the gate recess, and a contact recess is formed in a portion of the source/drain contact. A bi-stable resistive system (BRS) material is formed in the contact recess, and a metallization layer contact is formed upon the BRS material. A portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forms a reversible switch.
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公开(公告)号:US09620505B2
公开(公告)日:2017-04-11
申请号:US15073100
申请日:2016-03-17
发明人: Qing Liu , Xiuyu Cai , Ruilong Xie , Chun-chen Yeh , Kejia Wang , Daniel Chanemougame
IPC分类号: H01L21/30 , H01L27/088 , H01L27/12 , H01L29/66 , H01L21/84 , H01L29/06 , H01L29/161
CPC分类号: H01L27/0886 , H01L21/845 , H01L27/1211 , H01L29/0649 , H01L29/161 , H01L29/66795
摘要: A semiconductor device which includes: a substrate; a first set of fins above the substrate of a first semiconductor material; a second set of fins above the substrate and of a second semiconductor material different than the first semiconductor material; and an isolation region positioned between the first and second sets of fins, the isolation region having a nitride layer. The isolation region may be an isolation pillar or an isolation trench.
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公开(公告)号:US20150333086A1
公开(公告)日:2015-11-19
申请号:US14280998
申请日:2014-05-19
发明人: Qing LIU , Xiuyu CAI , Ruilong XIE , Chun-chen Yeh , Kejia Wang , Daniel Chanemougame
CPC分类号: H01L27/0886 , H01L21/845 , H01L27/1211 , H01L29/0649 , H01L29/161 , H01L29/66795
摘要: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.
摘要翻译: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物,以及在第二半导体区域上方并邻近间隔物形成第三半导体区域,其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分,从第一半导体区域形成第一组散热片,以及从第二和第三半导体区域形成第二组散热片。
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公开(公告)号:US11069744B2
公开(公告)日:2021-07-20
申请号:US16668116
申请日:2019-10-30
IPC分类号: H01L47/00 , H01L27/24 , H01L29/10 , H01L29/66 , H01L29/08 , H01L45/00 , H01L29/78 , H01L27/22
摘要: Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.
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