公开(公告)号：US20230378258A1

公开(公告)日：2023-11-23

申请号：US17663676

申请日：2022-05-17

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Anthony I. Chou ,  Brent A. Anderson ,  John Christopher Arnold ,  Junli Wang ,  Kai Zhao ,  Terence Hook ,  Julien Frougier ,  Xuefeng Liu

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/02 ,  H01L21/74

CPC classification number: H01L29/0665 ,  H01L21/76898 ,  H01L21/0237 ,  H01L21/0259 ,  H01L21/76829 ,  H01L21/743

Abstract: A method including forming an oxide layer on a first substrate and forming a second substrate on the oxide layer. Doping a first section of the second substrate while not doping a second section of the second substrate. Forming a first nano device on the second section of the second substrate and forming a second nano device on first section of the second substrate. Flipping the first substrate over to allow for backside processing of the substrate and forming at least one backside contact connected to the first nano device while backside contacts are not formed or connected to the second nano device.

公开(公告)号：US10374048B2

公开(公告)日：2019-08-06

申请号：US15813314

申请日：2017-11-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L29/423 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02 ,  H01L21/426 ,  H01L21/8234 ,  H01L21/3115 ,  H01L21/324 ,  H01L29/40 ,  H01L21/84 ,  H01L29/78 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/417

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20180277424A1

公开(公告)日：2018-09-27

申请号：US15989553

申请日：2018-05-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC: H01L21/762 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/225 ,  H01L21/265 ,  H01L21/28 ,  H01L29/51 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06 ,  H01L49/02 ,  H01L27/12 ,  H01L27/06 ,  H01L23/525 ,  H01L23/522 ,  H01L21/84 ,  H01L21/324 ,  H01L21/3213 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/161 ,  H01L29/24 ,  H01L21/763 ,  H01L27/08 ,  H01L29/16

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

公开(公告)号：US09721843B2

公开(公告)日：2017-08-01

申请号：US15076012

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/426 ,  H01L21/3115 ,  H01L21/324 ,  H01L21/84

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20170199532A1

公开(公告)日：2017-07-13

申请号：US15190254

申请日：2016-06-23

Applicant: International Business Machines Corporation

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Sungjae Lee

IPC: G05D23/24 ,  G01K7/16

CPC classification number: G05D23/24 ,  G01K7/16 ,  H01C3/04 ,  H01C17/232 ,  H01C17/267 ,  H01L22/14

Abstract: Embodiments include methods, computer systems and computer program products for controlling resistance value of a resistor in a circuit. Aspects include: retrieving, via a controller, a set of parameters of the resistor from a non-volatile memory in the circuit, detecting, via the controller, an operating temperature of the resistor during circuit operation in field using a temperature sensor, generating, by the controller, a temperature difference between operating temperature detected and a target temperature at which the resistor has a target resistance value, producing, by the controller, a control signal responsive to the temperature difference generated, and transmitting the control signal to a temperature regulator placed adjacent to the resistor to adjust the resistance value of the resistor. Resistance value of resistor varies in response to temperature changes around resistor according to a temperature coefficient of the resistance of the resistor. The temperature regulator may include a precision resistive heater.

公开(公告)号：US09685379B2

公开(公告)日：2017-06-20

申请号：US15159255

申请日：2016-05-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/265 ,  H01L21/426 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US09543213B2

公开(公告)日：2017-01-10

申请号：US15076021

申请日：2016-03-21

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Chung-Hsun Lin ,  Shreesh Narasimha ,  Claude Ortolland ,  Jonathan T. Shaw

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/40 ,  H01L29/51 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423 ,  H01L21/02 ,  H01L21/426 ,  H01L21/3115 ,  H01L21/324

CPC classification number: H01L21/28158 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02247 ,  H01L21/02255 ,  H01L21/02323 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31155 ,  H01L21/324 ,  H01L21/426 ,  H01L21/823462 ,  H01L21/845 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/511 ,  H01L29/512 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7856

Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.

公开(公告)号：US20240379658A1

公开(公告)日：2024-11-14

申请号：US18195701

申请日：2023-05-10

Applicant: International Business Machines Corporation

Inventor： Terence Hook ,  Anthony I. Chou

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/861

Abstract: A semiconductor structure including a stacked FET vertical diode is provided. The stacked FET vertical diode includes vertically stacked source/drain regions of opposite conductivity that are electrically connected by a semiconductor material layer that is positioned between the vertically stacked source/drain regions.

公开(公告)号：US20240105769A1

公开(公告)日：2024-03-28

申请号：US17935992

申请日：2022-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shahab Siddiqui ,  Ruqiang Bao ,  Charlotte DeWan Adams ,  Curtis S. Durfee ,  Anthony I. Chou ,  Barry Paul Linder ,  Ravikumar Ramachandran ,  Dechao Guo

IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7851

Abstract: A semiconductor device includes a substrate having a first region and a second region separated from the first region by distance to define a space therebetween. A first semiconductor device including a gate dielectric is on the first region. The first semiconductor device can implement a FinFet-based input/output (I/O) device in the first region. A second semiconductor device excluding a gate dielectric is on the second region. The second semiconductor device can implement a nanosheet-based logic device in the second region.

公开(公告)号：US20230411386A1

公开(公告)日：2023-12-21

申请号：US17807795

申请日：2022-06-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Albert M. Chu ,  Junli Wang ,  Brent A. Anderson ,  Anthony I. Chou ,  Dechao Guo

IPC: H01L27/088 ,  H01L23/535 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/088 ,  H01L23/535 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/66742 ,  H01L29/66439

Abstract: A microelectronic structure including a plurality of lower transistors and a plurality of upper transistors, where channels of the upper transistors are staggered from channels of the lower transistors. A lower dielectric pillar located beneath an upper transistor, where the dielectric pillar separates bottom transistors.