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    ASYMMETRIC STRESSOR DRAM
    7.
    发明申请
    ASYMMETRIC STRESSOR DRAM 有权
    不对称压力DRAM

    公开(公告)号：US20150349121A1

    公开(公告)日：2015-12-03

    申请号：US14476897

    申请日：2014-09-04

    Applicant: International Business Machines Corporation

    Inventor： Ravi K. Dasaka ,  Shreesh Narasimha ,  Ahmed Nayaz Noemaun ,  Karen A. Nummy ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang ,  Bidan Zhang

    IPC: H01L29/78 ,  H01L27/108

    CPC classification number: H01L29/7848 ,  H01L21/84 ,  H01L27/10829 ,  H01L27/10832 ,  H01L27/10867 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/66659

    Abstract: A stressor structure is formed within a drain region of an access transistor in a dynamic random access memory (DRAM) cell in a semiconductor-on-insulator (SOI) substrate without forming any stressor structure in a source region of the DRAM cell. The stressor structure induces a stress gradient within the body region of the access transistor, which induces a greater leakage current at the body-drain junction than at the body-source junction. The body potential of the access transistor has a stronger coupling to the drain voltage than to the source voltage. An asymmetric etch of a gate dielectric cap, application of a planarization material layer, and a non-selective etch of the planarization material layer and the gate dielectric cap can be employed to form the DRAM cell.

    Abstract translation: 在绝缘体上半导体（SOI）衬底中的动态随机存取存储器（DRAM）单元中的存取晶体管的漏极区域内形成应力器结构，而不在DRAM单元的源极区域中形成任何应力结构。 应力器结构在存取晶体管的体区内引起应力梯度，其在体 - 漏接点处比在体 - 源结处引起更大的漏电流。 存取晶体管的体电位与漏极电压的耦合比源电压更强。 栅极电介质盖的非对称蚀刻，平坦化材料层的施加以及平面化材料层和栅极电介质盖的非选择性蚀刻可用于形成DRAM单元。

    Low energy ion implantation of a junction butting region
    8.
    发明授权
    Low energy ion implantation of a junction butting region 有权
    结合对接区域的低能离子注入

    公开(公告)号：US09136321B1

    公开(公告)日：2015-09-15

    申请号：US14265410

    申请日：2014-04-30

    Applicant: International Business Machines Corporation

    Inventor： Shreesh Narasimha ,  Katsunori Onishi ,  Paul C. Parries ,  Chengwen Pei ,  Geng Wang

    IPC: H01L29/06 ,  H01L21/336 ,  H01L29/78 ,  H01L21/36 ,  H01L29/66

    CPC classification number: H01L27/10802 ,  H01L21/84 ,  H01L27/10891 ,  H01L27/1203 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/66636 ,  H01L29/78

    Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a junction butting region using low energy ion implantation to reduce parasitic leakage and body-to-body leakage between adjacent FETs that share a common contact in high density memory technologies, such as dynamic random access memory (DRAM) devices and embedded DRAM (eDRAM) devices. A method disclosed may include forming a junction butting region at the bottom of a trench formed in a semiconductor on insulator (SOI) layer using low energy ion implantation and protecting adjacent structures from damage from ion scattering using a protective layer.

    Abstract translation: 本发明一般涉及半导体器件，更具体地，涉及使用低能离子注入形成结对接区域以减少高密度共享公共接触的相邻FET之间的寄生泄漏和体对体泄漏的结构和方法 存储器技术，例如动态随机存取存储器（DRAM）器件和嵌入式DRAM（eDRAM）器件。 所公开的方法可以包括在使用低能离子注入的半导体绝缘体（SOI）层上形成的沟槽的底部形成接合对接区域，并使用保护层保护相邻结构免受离子散射的损害。

    Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels
    9.
    发明授权
    Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels 有权
    方面的本征外延缓冲层，用于减少短通道效应，同时最大化通道应力水平

    公开(公告)号：US08940595B2

    公开(公告)日：2015-01-27

    申请号：US13839741

    申请日：2013-03-15

    Applicant: International Business Machines Corporation

    Inventor： Bhupesh Chandra ,  Paul Chang ,  Gregory G. Freeman ,  Dechao Guo ,  Judson R. Holt ,  Arvind Kumar ,  Timothy J. McArdle ,  Shreesh Narasimha ,  Viorel Ontalus ,  Sangameshwar Rao Saudari ,  Christopher D. Sheraw ,  Matthew W. Stoker

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/7848 ,  H01L29/045 ,  H01L29/165 ,  H01L29/36 ,  H01L29/66636 ,  H01L29/7834

    Abstract: A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.

    Abstract translation: 通过选择性外延法将刻面的本征缓冲半导体材料沉积在源沟槽和漏极沟槽的侧壁上。 一个刻面邻接每个边缘，栅极间隔件的外侧壁邻接源沟槽或漏极沟槽的侧壁。 随后沉积掺杂的半导体材料以填充源极沟槽和漏极沟槽。 可以沉积掺杂的半导体材料，使得本征缓冲半导体材料的面被延伸，并且沉积的掺杂半导体材料的内壁在源极沟槽和漏极沟槽的每一个中融合。 掺杂的半导体材料随后可以向上生长。 方面的本征缓冲半导体材料部分允许在均匀宽度的区域中抑制掺杂剂的扩散，从而抑制短沟道效应，从而在小角部附近进一步扩散掺杂剂。

    Field effect transistor device having a hybrid metal gate stack
    10.
    发明授权
    Field effect transistor device having a hybrid metal gate stack 有权
    具有混合金属栅叠层的场效应晶体管器件

    公开(公告)号：US08836048B2

    公开(公告)日：2014-09-16

    申请号：US13653679

    申请日：2012-10-17

    Applicant: International Business Machines Corporation

    Inventor： Cyril Cabral, Jr. ,  Josephine B. Chang ,  Michael P. Chudzik ,  Martin M. Frank ,  Michael A. Guillorn ,  Christian Lavoie ,  Shreesh Narasimha ,  Vijay Narayanan

    IPC: H01L21/70

    CPC classification number: H01L29/78 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/66507 ,  H01L29/6659

    Abstract: A semiconductor device including a gate structure present on a channel portion of a semiconductor substrate and at least one gate sidewall spacer adjacent to the gate structure. In one embodiment, the gate structure includes a work function metal layer present on a gate dielectric layer, a metal semiconductor alloy layer present on a work function metal layer, and a dielectric capping layer present on the metal semiconductor alloy layer. The at least one gate sidewall spacer and the dielectric capping layer may encapsulate the metal semiconductor alloy layer within the gate structure.

    Abstract translation: 一种半导体器件，包括存在于半导体衬底的沟道部分上的栅极结构和邻近栅极结构的至少一个栅极侧壁间隔物。 在一个实施例中，栅极结构包括存在于栅极电介质层上的功函数金属层，存在于功函数金属层上的金属半导体合金层和存在于金属半导体合金层上的电介质覆盖层。 所述至少一个栅极侧壁间隔物和介电覆盖层可以将栅极结构内的金属半导体合金层封装。

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