公开(公告)号：US10593600B2

公开(公告)日：2020-03-17

申请号：US15051804

申请日：2016-02-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan

IPC: H01L21/8258 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/267 ,  H01L29/66 ,  H01L29/10 ,  H01L29/51

Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

公开(公告)号：US10580686B2

公开(公告)日：2020-03-03

申请号：US15989553

申请日：2018-05-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC: H01L21/762 ,  H01L29/06 ,  H01L23/522 ,  H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/84 ,  H01L23/525 ,  H01L27/12 ,  H01L29/423 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/225 ,  H01L21/324 ,  H01L27/08 ,  H01L21/763 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

公开(公告)号：US20200027779A1

公开(公告)日：2020-01-23

申请号：US16585314

申请日：2019-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC: H01L21/762 ,  H01L21/3213 ,  H01L49/02 ,  H01L27/06 ,  H01L21/8234 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/28 ,  H01L21/265 ,  H01L21/225 ,  H01L21/02 ,  H01L21/308 ,  H01L21/306 ,  H01L29/49 ,  H01L29/423 ,  H01L27/12 ,  H01L23/525 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/51 ,  H01L29/06 ,  H01L23/522

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

公开(公告)号：US10361304B2

公开(公告)日：2019-07-23

申请号：US16011124

申请日：2018-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Isaac Lauer ,  Jiaxing Liu ,  Renee T. Mo

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/10 ,  H01L21/324 ,  H01L21/306 ,  H01L21/84

Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

公开(公告)号：US20190181037A1

公开(公告)日：2019-06-13

申请号：US16274612

申请日：2019-02-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC: H01L21/762 ,  H01L21/8234 ,  H01L23/522 ,  H01L21/306 ,  H01L21/308 ,  H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/84 ,  H01L23/525 ,  H01L27/12 ,  H01L21/225 ,  H01L21/324 ,  H01L29/51

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

公开(公告)号：US10242906B2

公开(公告)日：2019-03-26

申请号：US15669260

申请日：2017-08-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC: H01L21/84 ,  H01L21/762 ,  H01L23/522 ,  H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/525 ,  H01L27/12 ,  H01L29/423 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/225 ,  H01L21/324 ,  H01L27/08 ,  H01L21/763 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.

公开(公告)号：US20180308844A1

公开(公告)日：2018-10-25

申请号：US16012032

申请日：2018-06-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan ,  John Rozen

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8258

CPC classification number: H01L27/0922 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/8258 ,  H01L27/092

Abstract: Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region, the second semiconductor region being formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A nitrogen-containing layer is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

公开(公告)号：US20170316979A1

公开(公告)日：2017-11-02

申请号：US15649122

申请日：2017-07-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Martin M. Frank ,  Renee T. Mo ,  Vijay Narayanan

IPC: H01L21/8258 ,  H01L29/20 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/51 ,  H01L29/16

CPC classification number: H01L21/8258 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/267 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66568

Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.

公开(公告)号：US09739728B1

公开(公告)日：2017-08-22

申请号：US15187467

申请日：2016-06-20

Applicant: International Business Machines Corporation

Inventor： Stephen W. Bedell ,  Renee T. Mo ,  Kunal Mukherjee ,  John A. Ott ,  Devendra K. Sadana ,  Brent A. Wacaser

IPC: G01N23/207 ,  G06K9/46

CPC classification number: G06K9/4671 ,  G01N23/203 ,  G01N2223/401 ,  G01N2223/6116 ,  G01N2223/646 ,  G06T7/0004

Abstract: Imaging and processing techniques are employed to identify crystalline defects obtained by ECCI from surrounding topography and is combined with defect counting and automatic classification.

公开(公告)号：US09698159B2

公开(公告)日：2017-07-04

申请号：US14864091

申请日：2015-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anthony I. Chou ,  Arvind Kumar ,  Renee T. Mo ,  Shreesh Narasimha

IPC: H01L27/11 ,  H01L27/12 ,  H01L23/522 ,  H01L21/762 ,  H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3213 ,  H01L29/06 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/84 ,  H01L23/525 ,  H01L29/423 ,  H01L21/306 ,  H01L21/308 ,  H01L21/8234 ,  H01L27/08 ,  H01L21/763 ,  H01L29/16 ,  H01L29/161 ,  H01L29/24

CPC classification number: H01L29/0649 ,  H01L21/02065 ,  H01L21/02181 ,  H01L21/2253 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28123 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3085 ,  H01L21/31053 ,  H01L21/31055 ,  H01L21/31116 ,  H01L21/32055 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/763 ,  H01L21/8234 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/5227 ,  H01L23/5256 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/08 ,  H01L27/1203 ,  H01L28/10 ,  H01L28/20 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/24 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L2924/00 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A metal-oxide-semiconductor field-effect transistor (MOSFET) with integrated passive structures and methods of manufacturing the same is disclosed. The method includes forming a stacked structure in an active region and at least one shallow trench isolation (STI) structure adjacent to the stacked structure. The method further includes forming a semiconductor layer directly in contact with the at least one STI structure and the stacked structure. The method further includes patterning the semiconductor layer and the stacked structure to form an active device in the active region and a passive structure of the semiconductor layer directly on the at least one STI structure.