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1.发明授权公开(公告)号：US10833150B2
公开(公告)日：2020-11-10
申请号：US16032632
申请日：2018-07-11
发明人： Martin M. Frank , Kam-Leung Lee , Eduard A. Cartier , Vijay Narayanan , Jean Fompeyrine , Stefan Abel , Oleg Gluschenkov , Hemanth Jagannathan
摘要： A method for converting a dielectric material including a type IV transition metal into a crystalline material that includes forming a predominantly non-crystalline dielectric material including the type IV transition metal on a supporting substrate as a component of an electrical device having a scale of microscale or less; and converting the predominantly non-crystalline dielectric material including the type IV transition metal to a crystalline crystal structure by exposure to energy for durations of less than 100 milliseconds and, in some instances, less than 10 microseconds. The resultant material is fully or partially crystallized and contains a metastable ferroelectric phase such as the polar orthorhombic phase of space group Pca21 or Pmn21. During the conversion to the crystalline crystal structure, adjacently positioned components of the electrical devices are not damaged.
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公开(公告)号：US10686039B2
公开(公告)日：2020-06-16
申请号：US16395024
申请日：2019-04-25
发明人： Martin M. Frank , Takashi Ando , Xiao Sun , Jin Ping Han , Vijay Narayanan
IPC分类号： H01L21/28 , H01L29/12 , H01L29/06 , H01L27/085 , H01L23/52 , H01L27/088 , H01L21/8234
摘要： Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.
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公开(公告)号：US20190130259A1
公开(公告)日：2019-05-02
申请号：US16232387
申请日：2018-12-26
摘要： Neural networks include neuron layers arranged in order from an input neuron layer to an output neuron layer, with at least one hidden layer between them. Weight arrays between respective pairs of neuron layers each include controllable resistance elements and AND gates configured to control addressing of the plurality of controllable resistance elements. Each controllable resistance element includes a junction field effect transistor configured to provide a resistance on a signal line and a first pass transistor configured to apply a charge increment or decrement to the junction field effect transistor responsive to a control pulse, such that the resistance on the signal line changes. The control pulse is only passed to a controllable resistance element when a respective AND gate is triggered. A training module is configured to train the neural network by adjusting resistances of the plurality of controllable resistance elements in each of the weight arrays.
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公开(公告)号：US10217745B2
公开(公告)日：2019-02-26
申请号：US15959832
申请日：2018-04-23
发明人： Takashi Ando , Martin M. Frank , Pranita Kerber , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/66 , H01L29/78 , H01L29/51 , H01L21/8238 , H01L29/49 , H01L21/8258 , H01L21/28
摘要： An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
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公开(公告)号：US10141333B1
公开(公告)日：2018-11-27
申请号：US15807625
申请日：2017-11-09
发明人： Martin M. Frank
IPC分类号： H01L27/1159 , G11C11/16 , G02F1/355 , H01L27/22
摘要： A ferroelectric device includes a first electrode and a second electrode that each comprise one or more electrically conductive layers. The ferroelectric device also includes a layer of ferroelectric material disposed between, and in electrical communication with, the first electrode and the second electrode. The first electrode and/or the second electrode include a recessed region and the layer of ferroelectric material includes a corresponding region of increased thickness that resists polarity changes. For example, a programming signal that is applied across the first and second electrodes may change a polarity of one or more other portions of the layer of ferroelectric material without changing a polarity of a portion of the layer of ferroelectric material that is proximate to the region of increased thickness. A corresponding method is also disclosed herein.
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公开(公告)号：US20180174847A1
公开(公告)日：2018-06-21
申请号：US15892884
申请日：2018-02-09
发明人： Takashi Ando , Robert H. Dennard , Martin M. Frank
IPC分类号： H01L21/28 , H01L21/8234 , H01L29/40 , H01L29/66 , H01L29/49 , H01L27/092 , H01L21/8238 , H01L21/02
CPC分类号： H01L21/28176 , H01L21/0223 , H01L21/02244 , H01L21/28 , H01L21/28247 , H01L21/823462 , H01L21/823857 , H01L21/823864 , H01L27/092 , H01L29/40 , H01L29/401 , H01L29/4983 , H01L29/51 , H01L29/512 , H01L29/6653 , H01L29/6656 , H01L29/78
摘要： A method for fabricating a semiconductor circuit includes obtaining a semiconductor structure having a gate stack of material layers including a high-k dielectric layer; oxidizing in a lateral manner the high-k dielectric layer, such that oxygen content of the high-k dielectric layer is increased first at the sidewalls of the high-k dielectric layer; and completing fabrication of a n-type field effect transistor from the gate stack after laterally oxidizing the high-k dielectric layer of the gate stack.
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公开(公告)号：US20170294586A1
公开(公告)日：2017-10-12
申请号：US15092894
申请日：2016-04-07
发明人： Martin M. Frank , Shu-Jen Han , George S. Tulevski
CPC分类号： H01L51/0049 , H01L51/0048 , H01L51/0575 , H01L51/102 , H01L2251/301 , H01L2251/303
摘要： A method of making a carbon nanotube structure includes depositing a first oxide layer on a substrate and a second oxide layer on the first oxide layer; etching a trench through the second oxide layer; removing end portions of the first oxide layer and portions of the substrate beneath the end portions to form cavities in the substrate; depositing a metal in the cavities to form first body metal pads; disposing a carbon nanotube on the first body metal pads and the first oxide layer such that ends of the carbon nanotube contact each of the first body metal layers; depositing a metal to form second body metal pads on the first body metal pads at the ends of the carbon nanotube; and etching to release the carbon nanotube, first body metal pads, and second body metal pads from the substrate, first oxide layer, and second oxide layer.
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公开(公告)号：US20170243789A1
公开(公告)日：2017-08-24
申请号：US15051804
申请日：2016-02-24
发明人： Takashi Ando , Martin M. Frank , Renee T. Mo , Vijay Narayanan
IPC分类号： H01L21/8258 , H01L29/16 , H01L21/8252 , H01L29/51 , H01L21/8238 , H01L27/092 , H01L29/20
摘要： Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
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9.发明授权Semiconductor devices containing an epitaxial perovskite/doped strontium titanate structure 有权含有外延钙钛矿/掺杂钛酸锶结构的半导体器件公开(公告)号：US09590100B2
公开(公告)日：2017-03-07
申请号：US14994821
申请日：2016-01-13
CPC分类号： H01L29/78391 , H01L21/28088 , H01L21/28291 , H01L29/4966 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/66545 , H01L29/6684
摘要： Semiconductor devices are provided such as, ferroelectric transistors and floating gate transistors, that include an epitaxial perovskite/doped strontium titanate structure formed above a surface of a semiconductor substrate. The epitaxial perovskite/doped strontium titanate structure includes a stack of, in any order, a doped strontium titanate and a perovskite type oxide.
摘要翻译： 提供了诸如铁电晶体管和浮栅晶体管的半导体器件，其包括在半导体衬底的表面上形成的外延钙钛矿/掺杂钛酸锶结构。 外延钙钛矿/掺杂的钛酸锶结构包括以任何顺序的掺杂的钛酸锶和钙钛矿型氧化物的叠层。
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公开(公告)号：US09287358B2
公开(公告)日：2016-03-15
申请号：US14221349
申请日：2014-03-21
IPC分类号： H01L29/06 , H01L29/423 , H01L29/78 , H01L27/12 , H01L29/49 , H01L29/66 , H01L21/84 , H01L21/3213 , H01L21/311 , B82Y10/00 , H01L29/40 , H01L29/775
CPC分类号： H01L29/0673 , B82Y10/00 , H01L21/31105 , H01L21/31111 , H01L21/32133 , H01L21/84 , H01L27/1203 , H01L29/401 , H01L29/41783 , H01L29/4232 , H01L29/42356 , H01L29/42364 , H01L29/4238 , H01L29/42392 , H01L29/49 , H01L29/66545 , H01L29/775 , H01L29/7842 , H01L29/78696
摘要： A disposable gate structure is formed over the alternating stack of first semiconductor material portions and second semiconductor material portions. The second semiconductor material portions are removed selective to the first semiconductor material portions to form suspended semiconductor nanowires. Isolated gate structures are formed in regions underlying the disposable gate structure by deposition and recessing of a first gate dielectric layer and a first gate conductor layer. After formation of a gate spacer, source regions, and drain regions, raised source and drain regions are formed on the source regions and the drain regions by selective deposition of a semiconductor material. The disposable gate structure is replaced with a replacement gate structure by deposition and patterning of a second gate dielectric layer and a second gate conductor layer. Distortion of the suspended semiconductor nanowires is prevented by the disposable gate structure and the isolated gate structures.
摘要翻译： 在第一半导体材料部分和第二半导体材料部分的交替堆叠上形成一次性栅极结构。 第二半导体材料部分被选择性地移除到第一半导体材料部分以形成悬浮的半导体纳米线。 隔离栅极结构通过第一栅极介电层和第一栅极导体层的沉积和凹陷形成在一次性栅极结构下面的区域中。 在形成栅极间隔物之后，通过选择性沉积半导体材料，在源极区和漏极区上形成源极区和漏极区。 一次性栅极结构通过第二栅极介电层和第二栅极导体层的沉积和图案化而被置换栅极结构代替。 通过一次性栅极结构和隔离的栅极结构来防止悬浮的半导体纳米线的失真。
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