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公开(公告)号：US09941363B2
公开(公告)日：2018-04-10
申请号：US14974162
申请日：2015-12-18
发明人： Cheng-Wei Cheng , Pranita Kerber , Amlan Majumdar , Yanning Sun
IPC分类号： H01L29/207 , H01L29/66 , H01L21/306 , H01L21/762 , H01L29/51 , H01L29/205 , H01L29/45 , H01L29/417 , H01L21/265 , H01L29/78
CPC分类号： H01L29/207 , H01L21/2654 , H01L21/26586 , H01L21/30612 , H01L21/76224 , H01L29/205 , H01L29/41783 , H01L29/452 , H01L29/511 , H01L29/665 , H01L29/66522 , H01L29/6653 , H01L29/6656 , H01L29/7834
摘要： A semiconductor device comprises a first layer of a substrate arranged on a second layer of the substrate the second layer of the substrate including a doped III-V semiconductor material barrier layer, a gate stack arranged on a channel region of the first layer of a substrate, a spacer arranged adjacent to the gate stack on the first layer of the substrate, an undoped epitaxially grown III-V semiconductor material region arranged on the second layer of the substrate, and an epitaxially grown source/drain region arranged on the undoped epitaxially grown III-V semiconductor material region, and a portion of the first layer of the substrate.
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公开(公告)号：US20170358579A1
公开(公告)日：2017-12-14
申请号：US15671695
申请日：2017-08-08
发明人： Takashi Ando , Martin M. Frank , Pranita Kerber , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/49 , H01L29/51 , H01L21/8238
CPC分类号： H01L27/0924 , H01L21/28255 , H01L21/28264 , H01L21/823821 , H01L21/823828 , H01L21/823857 , H01L21/8258 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66522 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
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公开(公告)号：US09812556B2
公开(公告)日：2017-11-07
申请号：US14142410
申请日：2013-12-27
发明人： Shogo Mochizuki , Gen Tsutsui , Raghavasimhan Sreenivasan , Pranita Kerber , Qiqing C. Ouyang , Alexander Reznicek
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method of manufacturing a semiconductor device includes forming a plurality of fin structures on a substrate, the plurality of fin structures including a diffusion region, forming an epitaxial layer on the plurality of fin structures in an area of the diffusion region such that a height of the upper surface of the epitaxial layer over plurality of fin structures is substantially equal to the height of the upper surface of the epitaxial layer between the plurality of fin structures, and planarizing the upper surface of the epitaxial layer by one of etch back and reflow annealing.
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公开(公告)号：US20170221898A1
公开(公告)日：2017-08-03
申请号：US15492463
申请日：2017-04-20
发明人： Takashi Ando , Martin M. Frank , Pranita Kerber , Vijay Narayanan
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/51 , H01L29/66 , H01L29/78 , H01L29/49
CPC分类号： H01L27/0924 , H01L21/28255 , H01L21/28264 , H01L21/823821 , H01L21/823828 , H01L21/823857 , H01L21/8258 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66522 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
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公开(公告)号：US20170117413A1
公开(公告)日：2017-04-27
申请号：US14921384
申请日：2015-10-23
IPC分类号： H01L29/78 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/7849 , H01L21/823807 , H01L21/823821 , H01L27/0924
摘要： A semiconductor structure includes a first fin structure having a first strain located on a surface of a first insulator layer portion. The first fin structure includes a first doped silicon germanium alloy fin portion having a first germanium content and a silicon germanium alloy fin portion having a third germanium content. A second fin structure having a second strain is located on a surface of a second insulator layer portion. The second fin structure includes a second doped silicon germanium alloy fin portion having a second germanium content and a silicon germanium alloy fin portion having the third germanium content, wherein the first germanium content differs from the second germanium content and the third germanium content is greater than the first and second germanium contents, and wherein the first strain differs from the second strain.
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公开(公告)号：US20170062602A1
公开(公告)日：2017-03-02
申请号：US15058421
申请日：2016-03-02
发明人： Jie Deng , Pranita Kerber , Qiqing C. Ouyang , Alexander Reznicek
CPC分类号： H01L29/1054 , H01L29/0649 , H01L29/1033 , H01L29/16 , H01L29/165 , H01L29/517 , H01L29/66545 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： A semiconductor device includes at least one semiconductor fin on an upper surface of a substrate. The at least one semiconductor fin includes a channel region interposed between opposing source/drain regions. A gate stack is on the upper surface of the substrate and wraps around sidewalls and an upper surface of only the channel region. The channel region is a dual channel region including a buried channel portion and a surface channel portion that completely surrounds the buried channel.
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7.发明申请HIGH-K GATE DIELECTRIC AND METAL GATE CONDUCTOR STACK FOR FIN-TYPE FIELD EFFECT TRANSISTORS FORMED ON TYPE III-V SEMICONDUCTOR MATERIAL AND SILICON GERMANIUM SEMICONDUCTOR MATERIAL 有权用于在III-V型半导体材料和硅锗半导体材料上形成的FIN型场效应晶体管的高K栅介质和金属栅导体堆叠公开(公告)号：US20170053915A1
公开(公告)日：2017-02-23
申请号：US14828202
申请日：2015-08-17
发明人： Takashi Ando , Martin M. Frank , Pranita Kerber , Vijay Narayanan
IPC分类号： H01L27/092 , H01L29/49 , H01L21/8238 , H01L29/51
CPC分类号： H01L27/0924 , H01L21/28255 , H01L21/28264 , H01L21/823821 , H01L21/823828 , H01L21/823857 , H01L21/8258 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/66522 , H01L29/66545 , H01L29/66795 , H01L29/6681 , H01L29/785
摘要： An electrical device that includes at least one n-type field effect transistor including a channel region in a type III-V semiconductor device, and at least one p-type field effect transistor including a channel region in a germanium containing semiconductor material. Each of the n-type and p-type semiconductor devices may include gate structures composed of material layers including work function adjusting materials selections, such as metal and doped dielectric layers. The field effect transistors may be composed of fin type field effect transistors. The field effect transistors may be formed using gate first processing or gate last processing.
摘要翻译： 一种电气装置，其包括至少一个n型场效应晶体管，其包括III-V族半导体器件中的沟道区，以及至少一个p型场效应晶体管，其包括含锗半导体材料中的沟道区。 n型和p型半导体器件中的每一个可以包括由包括功函数调整材料选择的材料层（例如金属和掺杂电介质层）组成的栅极结构。 场效应晶体管可以由鳍式场效应晶体管组成。 场效应晶体管可以使用栅极第一处理或栅极最后处理形成。
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公开(公告)号：US09530699B2
公开(公告)日：2016-12-27
申请号：US14984231
申请日：2015-12-30
IPC分类号： H01L21/8238 , H01L21/02 , H01L27/12 , H01L21/308 , H01L29/66 , H01L21/84 , H01L21/306 , H01L27/092
CPC分类号： H01L21/823821 , H01L21/02532 , H01L21/30604 , H01L21/308 , H01L21/823807 , H01L21/823814 , H01L21/823828 , H01L21/845 , H01L27/0922 , H01L27/0924 , H01L27/1211 , H01L29/66 , H01L29/6681
摘要： A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.
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9.发明授权FinFET device with vertical silicide on recessed source/drain epitaxy regions 有权FinFET器件，垂直硅化物在凹陷源极/漏极外延区域公开(公告)号：US09391173B2
公开(公告)日：2016-07-12
申请号：US14583454
申请日：2014-12-26
IPC分类号： H01L21/336 , H01L29/66 , H01L29/78 , H01L29/08
CPC分类号： H01L29/41791 , H01L21/28518 , H01L21/76805 , H01L21/76895 , H01L23/535 , H01L27/0886 , H01L29/0847 , H01L29/16 , H01L29/1608 , H01L29/161 , H01L29/165 , H01L29/45 , H01L29/456 , H01L29/665 , H01L29/66545 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785 , H01L29/7851
摘要： A method of forming a semiconductor device that includes forming a fin structure from a semiconductor substrate, and forming a gate structure on a channel region portion of the fin structure. A source region and a drain region are formed on a source region portion and a drain region portion of the fin structure on opposing sides of the channel portion of the fin structure. At least one sidewall of the source region portion and the drain region portion of the fin structure is exposed. A metal semiconductor alloy is formed on the at least one sidewall of the source region portion and the drain region portion of the fin structure that is exposed.
摘要翻译： 一种形成半导体器件的方法，包括从半导体衬底形成鳍结构，并且在鳍结构的沟道区部分上形成栅极结构。 源极区域和漏极区域在翅片结构的沟道部分的相对侧上的翅片结构的源极区域和漏极区域部分上形成。 源区域部分的至少一个侧壁和翅片结构的漏极区域部分被暴露。 金属半导体合金形成在被暴露的鳍状结构的源区域部分和漏极区域的至少一个侧壁上。
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公开(公告)号：US09385237B2
公开(公告)日：2016-07-05
申请号：US14687210
申请日：2015-04-15
发明人： Pranita Kerber , Viorel Ontalus , Donald R. Wall , Zhengmao Zhu
IPC分类号： H01L29/16 , H01L29/786 , H01L21/8234 , H01L29/66 , H01L29/08 , H01L29/165 , H01L29/417 , H01L29/06 , H01L29/167 , H01L29/78
CPC分类号： H01L29/0847 , H01L21/823412 , H01L29/0649 , H01L29/165 , H01L29/167 , H01L29/41783 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66575 , H01L29/66628 , H01L29/66772 , H01L29/78 , H01L29/7834 , H01L29/78618 , H01L29/78687 , H01L2029/7858
摘要： Carbon-doped semiconductor material portions are formed on a subset of surfaces of underlying semiconductor surfaces contiguously connected to a channel of a field effect transistor. Carbon-doped semiconductor material portions can be formed by selective epitaxy of a carbon-containing semiconductor material layer or by shallow implantation of carbon atoms into surface portions of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions can be deposited as layers and subsequently patterned by etching, or can be formed after formation of disposable masking spacers. Raised source and drain regions are formed on the carbon-doped semiconductor material portions and on physically exposed surfaces of the underlying semiconductor surfaces. The carbon-doped semiconductor material portions locally retard dopant diffusion from the raised source and drain regions into the underlying semiconductor material regions, thereby enabling local tailoring of the dopant profile, and alteration of device parameters for the field effect transistor.
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