公开(公告)号：US20230290776A1

公开(公告)日：2023-09-14

申请号：US17654412

申请日：2022-03-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Shogo Mochizuki ,  Sanjay C. Mehta

IPC: H01L27/088 ,  H01L27/12 ,  H01L21/822 ,  H01L21/84

CPC classification number: H01L27/088 ,  H01L27/1207 ,  H01L21/8221 ,  H01L21/84

Abstract: A lower nanosheet stack including alternating layers of a first work function metal and a semiconductor channel material, an upper nanosheet stack including alternating layers of a second work function metal and the semiconductor channel material, one or more dielectric layers between the lower nanosheet stack and the upper nanosheet stack, each separated by an inner spacer. An embodiment where the one or more partial dielectric layers each include an opening. Forming an upper nanosheet stack vertically aligned above an intermediate stack, vertically aligned above a lower nanosheet stack, the upper nanosheet stack, the lower nanosheet stack each including alternating layers of a first sacrificial material and a semiconductor channel material, the intermediate stack including one or more alternating layers of the sacrificial material and a second sacrificial material, recessing the second sacrificial material; and forming second inner spacers where the second sacrificial material was recessed.

公开(公告)号：US20230085288A1

公开(公告)日：2023-03-16

申请号：US17472858

申请日：2021-09-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Injo Ok ,  Timothy Mathew Philip ,  Kevin W. Brew ,  Muthumanickam Sankarapandian ,  Steven Michael McDermott ,  Nicole Saulnier ,  Andrew Herbert Simon ,  Sanjay C. Mehta

IPC: H01L45/00

Abstract: A semiconductor structure includes a heater located in a first layer of a device, wherein the heater is surrounded by a dielectric, a phase change memory (PCM) liner in direct contact with a top surface of the heater in a second layer of the device, a spacer disposed adjacent the PCM liner in the second layer of the device, and a PCM stack disposed above the PCM liner in the second layer of the device.

公开(公告)号：US11456415B2

公开(公告)日：2022-09-27

申请号：US17114594

申请日：2020-12-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Injo Ok ,  Ruqiang Bao ,  Andrew Herbert Simon ,  Kevin W. Brew ,  Nicole Saulnier ,  Iqbal Rashid Saraf ,  Muthumanickam Sankarapandian ,  Sanjay C. Mehta

IPC: H01L45/00 ,  H01L27/24

Abstract: A semiconductor structure may include a heater surrounded by a dielectric layer, a projection liner on top of the heater, a phase change material layer above the projection liner, and a top electrode contact surrounding a top portion of the phase change material layer, The projection liner may cover a top surface of the heater. The projection liner may separate the phase change material layer from the second dielectric layer and the heater. The projection liner may provide a parallel conduction path in the crystalline phase and the amorphous phase of the phase change material layer. The top electrode contact may be separated from the phase change material layer by a metal liner. The semiconductor structure may include a bottom electrode below and in electrical contact with the heater and a top electrode above and in electrical contact with the phase change material layer.

公开(公告)号：US11264569B2

公开(公告)日：2022-03-01

申请号：US16671748

申请日：2019-11-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Injo Ok ,  Kevin W. Brew ,  Timothy M. Philip ,  Muthumanickam Sankarapandian ,  Sanjay C. Mehta ,  Nicole Saulnier ,  Steven M. Mcdermott

IPC: H01L45/00 ,  G11C13/00

Abstract: A phase change material memory device is provided. The phase change material memory device includes one or more electrical contacts in a substrate, and a dielectric cover layer on the electrical contacts and substrate. The phase change material memory device further includes a lower conductive shell in a trench above one of the one or more electrical contacts, and an upper conductive shell on the lower conductive shell in the trench. The phase change material memory device further includes a conductive plug filling the upper conductive shell. The phase change material memory device further includes a liner layer on the dielectric cover layer and conductive plug, and a phase change material block on the liner layer on the dielectric cover layer and in the trench.

公开(公告)号：US10692985B2

公开(公告)日：2020-06-23

申请号：US16282607

申请日：2019-02-22

Applicant: International Business Machines Corporation

Inventor： Nicolas J. Loubet ,  Sanjay C. Mehta ,  Vijay Narayanan ,  Muthumanickam Sankarapandian

IPC: H01L29/00 ,  H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66 ,  H01L29/10 ,  H01L29/775 ,  B82Y10/00

Abstract: A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes forming a stack of silicon nanosheets above a substrate forming an interfacial layer over the nanosheets depositing a high-k dielectric layer conformally on the interfacial layer. The method also includes depositing a layer of silicon nitride (SiN) above the high-k dielectric layer and performing reliability anneal after depositing the layer of SiN to crystalize the high-k dielectric layer.

公开(公告)号：US10651308B2

公开(公告)日：2020-05-12

申请号：US16043637

申请日：2018-07-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Oleg Gluschenkov ,  Sanjay C. Mehta ,  Shogo Mochizuki ,  Alexander Reznicek

IPC: H01L29/76 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/306 ,  H01L21/02 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165

Abstract: A method of forming a semiconductor device that includes providing a vertically orientated channel region; and converting a portion of an exposed source/drain contact surface of the vertically orientated channel region into an amorphous crystalline structure. The amorphous crystalline structure is from the vertically orientated channel region. An in-situ doped extension region is epitaxially formed on an exposed surface of the vertically orientated channel region. A source/drain region is epitaxially formed on the in-situ doped extension region.

公开(公告)号：US10580854B2

公开(公告)日：2020-03-03

申请号：US15787065

申请日：2017-10-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Sanjay C. Mehta ,  Xin Miao ,  Chun-Chen Yeh

IPC: H01L21/02 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49

Abstract: A method of forming a punch through stop region in a fin structure is disclosed. The method may include forming a doped glass layer on a fin structure and forming a masking layer on the doped glass layer. The method may further include removing a portion of the masking layer from an active portion of the fin structure, and removing an exposed portion the doped glass layer that is present on the active portion of the fin structure. A remaining portion of the doped glass layer is present on the isolation portion of the fin structure. Dopant from the doped glass layer may then be diffused into the isolation portion of the fin structure to form the punch through stop region between the active portion of the fin structure and a supporting substrate.

公开(公告)号：US10366988B2

公开(公告)日：2019-07-30

申请号：US14826956

申请日：2015-08-14

Applicant: International Business Machines Corporation

Inventor： Sanjay C. Mehta ,  Alexander Reznicek

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/283 ,  H01L21/02 ,  H01L29/08 ,  H01L29/45 ,  H01L21/8234 ,  H01L29/04

Abstract: A semiconductor structure includes a plurality of semiconductor material fins located on a surface of a substrate. At least one gate structure straddles over a portion of each semiconductor material fin. Unmerged source-side epitaxial semiconductor material portions are located on an exposed surfaces of each semiconductor material fin and on one side of each gate structure and unmerged drain-side epitaxial semiconductor portions are located on other exposed surfaces of each semiconductor material fin and on another side of each gate structure. An etch stop structure is located between each unmerged source-side and drain-side epitaxial semiconductor material portions. Each etch stop structure includes a bottom material portion that has a higher etch resistance in a specific etchant as compared to an upper material portion of the etch stop structure.

公开(公告)号：US10332977B2

公开(公告)日：2019-06-25

申请号：US15880059

申请日：2018-01-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Su Chen Fan ,  Andre P. Labonte ,  Lars W. Liebmann ,  Sanjay C. Mehta

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/027 ,  H01L23/535 ,  H01L27/11 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner spacers on the gate spacers; etching contact openings adjacent to sides of the gate structure down to a substrate below the gate structures; and forming trench contacts on sides of the gate structure. An interlevel dielectric (ILD) is deposited on the gate conductor and the trench contacts and over the gate structure. The ILD is opened up to expose the trench contact on one side of the gate structure and the gate conductor. A second conductive material provides a self-aligned contact down to the trench contact on the one side and to form a gate contact down to the gate conductor and a horizontal connection within the ILD over an active area between the gate conductor and the self-aligned contact.

公开(公告)号：US10115629B2

公开(公告)日：2018-10-30

申请号：US15789416

申请日：2017-10-20

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Thomas J. Haigh ,  Juntao Li ,  Eric G. Liniger ,  Sanjay C. Mehta ,  Son V. Nguyen ,  Chanro Park ,  Tenko Yamashita

IPC: H01L29/78 ,  H01L21/768 ,  H01L21/02 ,  H01L23/528 ,  H01L23/532 ,  H01L29/417 ,  H01L29/66 ,  H01L29/49

Abstract: Semiconductor devices having air gap spacers that are formed as part of BEOL or MOL layers of the semiconductor devices are provided, as well as methods for fabricating such air gap spacers. For example, a method comprises forming a first metallic structure and a second metallic structure on a substrate, wherein the first and second metallic structures are disposed adjacent to each other with insulating material disposed between the first and second metallic structures. The insulating material is etched to form a space between the first and second metallic structures. A layer of dielectric material is deposited over the first and second metallic structures using a pinch-off deposition process to form an air gap in the space between the first and second metallic structures, wherein a portion of the air gap extends above an upper surface of at least one of the first metallic structure and the second metallic structure.