公开(公告)号：US12068166B2

公开(公告)日：2024-08-20

申请号：US18307798

申请日：2023-04-27

申请人： FILNEX INC.

发明人： Mitsuhiko Ogihara

IPC分类号： H01L21/306 ,  H01L21/02 ,  H01L21/20

CPC分类号： H01L21/306 ,  H01L21/02112 ,  H01L21/02667 ,  H01L21/20

摘要： A method for manufacturing a semiconductor device includes the steps of forming a fixing layer, coupling a third substrate different from the first substrate and the second substrate to the fixing layer, separating the semiconductor thin film layer from the first substrate by moving the third substrate away from the base material substrate with the third substrate coupled to the coupling region, and bonding the semiconductor thin film layer to the second substrate after separation from the base material substrate, wherein the forming the fixing layer forms the fixing layer having a thickness such that a crack is generated between the fixing layer formed on the first substrate and the fixing layer formed on a side surface of the semiconductor thin film layer by a force for moving the third substrate.

公开(公告)号：US11855188B2

公开(公告)日：2023-12-26

申请号：US17809963

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

IPC分类号： H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

CPC分类号： H01L29/66795 ,  H01L21/20 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/785

摘要： A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

公开(公告)号：US20180334757A1

公开(公告)日：2018-11-22

申请号：US15757879

申请日：2016-09-07

申请人： Shin-Etsu Chemical Co., Ltd. ,  CUSIC Inc.

发明人： Yoshihiro Kubota ,  Shoji Akiyama ,  Hiroyuki Nagasawa

IPC分类号： C30B25/20 ,  H01L21/02 ,  H01L21/78 ,  C30B29/36 ,  C30B29/68 ,  C30B25/18

CPC分类号： C30B25/20 ,  C30B25/186 ,  C30B29/36 ,  C30B29/68 ,  H01L21/02 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02529 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02634 ,  H01L21/02658 ,  H01L21/20 ,  H01L21/7806

摘要： Provided is a method for manufacturing an SiC composite substrate 10 having a single-crystal SiC layer 12 on a polycrystalline SiC substrate 11, wherein: the single-crystal SiC layer 12 is provided on one surface of a holding substrate 21 comprising Si, and a single-crystal SiC-layer carrier 14 is prepared; polycrystalline SiC is then accumulated on the single-crystal SiC layer 12 by a physical or chemical means, and an SiC laminate 15 is prepared in which the single-crystal SiC layer 12 and the polycrystalline SiC substrate 11 are laminated on the holding substrate 21; and the holding substrate 21 is then physically and/or chemically removed. With the present invention, an SiC composite substrate having a single-crystal. SiC layer with good crystallinity is obtained with a simple manufacturing process.

公开(公告)号：US20180330765A1

公开(公告)日：2018-11-15

申请号：US16042894

申请日：2018-07-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Yen-Huei CHEN ,  Chien Chi Linus TIEN ,  Kao-Cheng LIN ,  Jung-Hsuan CHEN

IPC分类号： G11C7/06 ,  H01L29/06 ,  H01L27/11 ,  H01L23/552 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/02 ,  G11C11/419 ,  H01L23/528 ,  H01L21/20 ,  H01L27/092

CPC分类号： G11C7/065 ,  G11C11/419 ,  H01L21/20 ,  H01L21/2003 ,  H01L21/28008 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L23/552 ,  H01L27/0207 ,  H01L27/0296 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/0649

摘要： A sense amplifier (SA) comprises a semiconductor substrate having an oxide definition (OD) region, a pair of SA sensing devices, a SA enabling device, and a sense amplifier enabling signal (SAE) line for carrying an SAE signal. The pair of SA sensing devices have the same poly gate length Lg as the SA enabling device, and they all share the same OD region. When enabled, the SAE signal turns on the SA enabling device to discharge one of the pair of SA sensing devices for data read from the sense amplifier.

公开(公告)号：US10030318B2

公开(公告)日：2018-07-24

申请号：US14969809

申请日：2015-12-15

申请人： NGK INSULATORS, LTD.

发明人： Yoshitaka Kuraoka ,  Yasunori Iwasaki ,  Takashi Yoshino

IPC分类号： C30B19/02 ,  C30B9/12 ,  C30B19/12 ,  C30B29/40 ,  H01L21/02 ,  C30B25/18 ,  H01L33/00 ,  C30B29/38 ,  H01L21/20 ,  H01L21/208

CPC分类号： C30B19/02 ,  C30B9/12 ,  C30B19/12 ,  C30B25/18 ,  C30B25/186 ,  C30B29/38 ,  C30B29/406 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02645 ,  H01L21/02658 ,  H01L21/20 ,  H01L21/208 ,  H01L33/007

摘要： A composite substrate includes a polycrystalline ceramic substrate, a silicon substrate directly bonded to the polycrystalline ceramic substrate, a seed crystal film formed on the silicon substrate by vapor phase process and made of a nitride of a group 13 element, and a gallium nitride crystal layer grown on the seed crystal film by flux method.

公开(公告)号：US20180204722A1

公开(公告)日：2018-07-19

申请号：US15915828

申请日：2018-03-08

申请人： MIE UNIVERSITY

发明人： Hideto Miyake

IPC分类号： H01L21/02 ,  H01L21/324

CPC分类号： C23C16/18 ,  C23C16/34 ,  C30B29/38 ,  C30B29/406 ,  H01L21/02172 ,  H01L21/02205 ,  H01L21/02304 ,  H01L21/02389 ,  H01L21/0254 ,  H01L21/20 ,  H01L21/205 ,  H01L21/324 ,  H01L21/3245

摘要： A method for manufacturing a nitride semiconductor substrate includes: a preparation step of preparing a sapphire substrate (2); and a buffer layer forming step of forming an AlN buffer layer on the sapphire substrate, wherein the buffer layer forming step includes: a group III nitride semiconductor forming step of forming a precursor of an AlN buffer layer on the sapphire substrate; and an annealing step of annealing the sapphire substrate on which the precursor of the AIN buffer layer is formed in a gas-tight state in which a principal surface of the precursor of the AlN buffer layer is covered with a cover member (such as a sapphire substrate) for inhibiting a component of the group III nitride semiconductor from dissociating from the principal surface of the formed precursor of the AlN buffer layer.

公开(公告)号：US20180033907A1

公开(公告)日：2018-02-01

申请号：US15551960

申请日：2016-02-08

申请人： Yoshikatsu MORISHIMA ,  Kazuyuki IIZUKA ,  Akito KURAMATA ,  Hideki HIRAYAMA

发明人： Yoshikatsu MORISHIMA ,  Kazuyuki IIZUKA ,  Akito KURAMATA ,  Hideki HIRAYAMA

IPC分类号： H01L33/00 ,  C30B29/40 ,  H01L33/32 ,  C30B25/18 ,  H01L33/02 ,  H01L33/12 ,  C30B29/16 ,  C30B29/68

CPC分类号： H01L33/007 ,  C30B25/18 ,  C30B25/183 ,  C30B29/16 ,  C30B29/38 ,  C30B29/406 ,  C30B29/68 ,  H01L21/20 ,  H01L21/205 ,  H01L33/025 ,  H01L33/12 ,  H01L33/32

摘要： A nitride semiconductor template includes a Ga2O3 substrate, a buffer layer formed on the Ga2O3 substrate and including AlN as a principal component, a first nitride semiconductor layer formed on the buffer layer and including AlxGa1-xN (0.2

公开(公告)号：US20170330757A1

公开(公告)日：2017-11-16

申请号：US15594482

申请日：2017-05-12

申请人： OSRAM Opto Semiconductors GmbH

发明人： Christoph EICHLER ,  Andre SOMERS ,  Harald KOENIG ,  Bernhard STOJETZ ,  Andreas LOEFFLER ,  Alfred LELL

IPC分类号： H01L21/268 ,  H01L21/324 ,  H01L21/3105

CPC分类号： H01L27/1285 ,  H01L21/02104 ,  H01L21/02293 ,  H01L21/02365 ,  H01L21/0254 ,  H01L21/02617 ,  H01L21/02636 ,  H01L21/02647 ,  H01L21/20 ,  H01L21/2022 ,  H01L21/268 ,  H01L21/3105 ,  H01L21/3247 ,  H01L21/76248 ,  H01L21/76272 ,  H01L27/1281 ,  H01L33/007 ,  H01L33/025 ,  H01L33/08 ,  H01L33/12 ,  H01L2933/0016 ,  H01S5/2068 ,  H01S5/2077 ,  H01S5/222 ,  H01S5/223 ,  H01S2304/00

摘要： A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.

公开(公告)号：US20170250073A1

公开(公告)日：2017-08-31

申请号：US15595503

申请日：2017-05-15

申请人： International Business Machines Corporation

发明人： Takashi Ando ,  Eduard A. Cartier ,  Michael P. Chudzik ,  Aritra Dasgupta ,  Herbert L. Ho ,  Donghun Kang ,  Rishikesh Krishnan ,  Vijay Narayanan ,  Kern Rim

IPC分类号： H01L21/02 ,  H01L21/20 ,  H01G4/005 ,  H01L21/322

CPC分类号： H01L21/02365 ,  H01G4/005 ,  H01L21/02178 ,  H01L21/02617 ,  H01L21/20 ,  H01L21/3221 ,  H01L23/26 ,  H01L27/10861 ,  H01L27/1087 ,  H01L28/60 ,  H01L28/90 ,  H01L29/66181 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method including forming an oxygen gettering layer on one side of an insulating layer of a deep trench capacitor between the insulating layer and a substrate, the oxygen gettering layer including an aluminum containing compound, and depositing an inner electrode on top of the insulating layer, the inner electrode including a metal.

公开(公告)号：US20170236948A1

公开(公告)日：2017-08-17

申请号：US15583726

申请日：2017-05-01

申请人： V TECHNOLOGY CO., LTD.

发明人： Michinobu MIZUMURA ,  Makoto HATANAKA ,  Tetsuya KIGUCHI

IPC分类号： H01L29/786 ,  H01L21/02 ,  H01L21/67 ,  H01L29/66

CPC分类号： H01L29/78678 ,  H01L21/02675 ,  H01L21/20 ,  H01L21/67115 ,  H01L27/1281 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78621

摘要： The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.