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    SEMICONDUCTOR MEMORY WITH RESPECTIVE POWER VOLTAGES FOR MEMORY CELLS
    3.
    发明申请
    SEMICONDUCTOR MEMORY WITH RESPECTIVE POWER VOLTAGES FOR MEMORY CELLS 审中-公开

    公开(公告)号：US20180277199A1

    公开(公告)日：2018-09-27

    申请号：US15991739

    申请日：2018-05-29

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Cheng WU ,  Chih-Yu LIN ,  Kao-Cheng LIN ,  Wei-Min CHAN ,  Yen-Huei CHEN

    IPC: G11C11/419

    Abstract: A device is disclosed that includes a plurality of first memory cells, a plurality of second memory cells, a power circuit, and a header circuit. The power circuit us configured to provide the first power voltage for the plurality of first memory cells, and to provide the second power voltage, that is independent from the first power voltage, for the plurality of second memory cells. The header circuit is configured to provide, during the write operation, the first voltage smaller than the first power voltage, the second power voltage, or the combination thereof, for corresponding memory cells of the plurality of first memory cells and the plurality of second memory cells.

    SEMICONDUCTOR MEMORY
    5.
    发明申请
    SEMICONDUCTOR MEMORY 有权

    公开(公告)号：US20170178719A1

    公开(公告)日：2017-06-22

    申请号：US15336633

    申请日：2016-10-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Wei-Cheng WU ,  Chih-Yu LIN ,  Kao-Cheng LIN ,  Wei-Min CHAN ,  Yen-Huei CHEN

    IPC: G11C11/419

    CPC classification number: G11C11/419

    Abstract: A device is disclosed that includes first memory cells, second memory cells, a first conductive line and a second conductive line. The first conductive line is electrically disconnected from the second conductive line. The first conductive line receives a first power voltage for the plurality of first memory cells. The second conductive line receives a second power voltage that is independent from the first power voltage, for the plurality of second memory cells.

    DUAL PORT SRAM WITH DUMMY READ RECOVERY
    8.
    发明申请
    DUAL PORT SRAM WITH DUMMY READ RECOVERY 有权
    双端口SRAM与DUMMY READ RECOVERY

    公开(公告)号：US20150092476A1

    公开(公告)日：2015-04-02

    申请号：US14043869

    申请日：2013-10-02

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kao-Cheng LIN ,  Wei Min CHAN ,  Yen-Huei CHEN

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/412

    Abstract: An integrated includes a dual port memory cell such as a SRAM cell. A first port dummy read recovery block couples the first port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the second port bit line, and couples the first port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the second port complementary bit line. A second port dummy read recovery block couples the second port complementary bit line to a high voltage supply node during a write logic low operation to the data node through the first port bit line, and couples the second port bit line to a high voltage supply node during a write logic low operation to the complementary data node through the first port complementary bit line.

    Abstract translation: 集成的包括诸如SRAM单元的双端口存储单元。 第一端口虚拟读取恢复块在写入逻辑低操作期间通过第二端口位线将第一端口互补位线耦合到高电压供应节点到数据节点，并且将第一端口位线耦合到高电压供应节点 在通过第二端口互补位线到互补数据节点的写入逻辑低操作期间。 第二端口虚拟读恢复块在写逻辑低操作期间通过第一端口位线将第二端口互补位线耦合到高电压电源节点，并将第二端口位线耦合到高电压电源节点 在通过第一端口互补位线到互补数据节点的写入逻辑低操作期间。

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