公开(公告)号：US20240071559A1

公开(公告)日：2024-02-29

申请号：US18243054

申请日：2023-09-06

申请人： Rambus Inc.

发明人： Adrian E. Ong ,  Fan Ho

IPC分类号： G11C29/00 ,  G11C11/401 ,  G11C11/408 ,  G11C29/02 ,  G11C29/04 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48

CPC分类号： G11C29/76 ,  G11C11/401 ,  G11C11/4085 ,  G11C29/027 ,  G11C29/04 ,  G11C29/12 ,  G11C29/4401 ,  G11C29/48 ,  G11C29/78 ,  G11C29/802 ,  G11C29/789 ,  G11C2229/743

摘要： A dynamic random access memory (DRAM) comprises a plurality of primary data storage elements, a plurality of redundant data storage elements, and circuitry to receive a first register setting command and initiate a repair mode in the DRAM in response to the first register setting command. The circuitry is further to receive an activation command, repair a malfunctioning row address in the DRAM, receive a precharge command, receive a second register setting command, terminate the repair mode in the DRAM in response to the second register setting command, receive a memory access request for data stored at the malfunctioning row address, and redirect the memory access request to a corresponding row address in the plurality of redundant data storage elements.

公开(公告)号：US11250928B2

公开(公告)日：2022-02-15

申请号：US17100647

申请日：2020-11-20

申请人： Micron Technology, Inc.

发明人： Michael Richard Spica

IPC分类号： G11C29/38 ,  G11C29/36 ,  G01R31/3177 ,  G01R31/3185 ,  G11C29/32 ,  G01R31/317 ,  G11C29/48

摘要： A system comprises a testing mode register, a set of pins, and a test access port controller. The test access port controller initiates a first testing mode by configuring the set of pins according to a first pin protocol. The test access port controller configures a first pin to receive first test pattern data based on a first convention and configures a second pin to output first test result data based on the first test pattern data. Based on detecting a register command stored in the testing mode register, the test access port controller initiates a second testing mode by configuring the set of pins according to a second pin protocol. The test access port controller configures the first pin to receive a second test pattern data generated based on a second convention and configures the second pin to output a second test result data based on the second test pattern data.

公开(公告)号：US20220005541A1

公开(公告)日：2022-01-06

申请号：US16919922

申请日：2020-07-02

申请人： Micron Technology, Inc.

发明人： Jason M. Johnson ,  Dennis G. Montierth

IPC分类号： G11C29/44 ,  G11C29/46 ,  G11C29/42 ,  G11C29/48

摘要： Methods of testing memory devices are disclosed. A method may include reading from a number of memory addresses of a memory array of the memory device and identifying each memory address of the number of addresses as either a pass or a fail. The method may further include storing, for each identified fail, data associated with the identified fail in a buffer of the memory device. Further, the method may include conveying, to a tester external to the memory device, at least some of the data associated with each identified fail without conveying address data associated with each identified pass to the tester. Devices and systems are also disclosed.

公开(公告)号：US11037651B2

公开(公告)日：2021-06-15

申请号：US16675676

申请日：2019-11-06

申请人： QUALCOMM Incorporated

发明人： Arvind Jain ,  Anju George ,  Swayam Pattnaik

IPC分类号： G11C29/00 ,  G11C29/56 ,  G11C29/48 ,  G11C29/14 ,  G11C29/32

摘要： Disclosed are methods and apparatus for securely accessing and testing a double data rate (DDR) memory device. The apparatus includes a first memory test access port (TAP) configured to enable or disable access to at least one double date rate (DDR) memory device, a second memory TAP configured to enable or disable access to at least one non-DDR memory device, and a test controller configured to test the at least one DDR memory device via the first memory TAP or test the at least one non-DDR memory device via the second memory TAP. In an aspect, at least one non-DDR memory device contains proprietary information. Accordingly, access to the at least one non-DDR memory device via the second memory TAP is disabled when access to the at least one DDR memory device via the first memory TAP is enabled.

公开(公告)号：US10998079B2

公开(公告)日：2021-05-04

申请号：US16867287

申请日：2020-05-05

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Jong Jun Kim ,  Feng Pan ,  Jong Seuk Lee ,  Zhenyu Lu ,  Yongna Li ,  Lidong Song ,  Youn Cheul Kim ,  Steve Weiyi Yang ,  Simon Shi-Ning Yang

IPC分类号： G11C29/00 ,  G11C29/50 ,  G11C29/48 ,  H01L27/11526 ,  H01L27/11573 ,  G11C29/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11578 ,  G11C29/12 ,  G11C29/56 ,  H01L27/11551 ,  G11C29/04

摘要： Embodiments of methods for testing three-dimensional memory devices are disclosed. The method can include: applying an input signal to a first conductive pad of the memory device by a first probe of a probe card; transmitting the input signal through the first conductive pad, a first TAC, a first interconnect structure passing through a bonding interface of the memory device, at least one of a memory array contact and a test circuit to a test structure; receiving an output signal through a second interconnect structure passing through the bonding interface, a second TAC, at least one of the memory array contact and the test circuit from the test structure; measuring the output signal from a second conductive pad of the memory device by a second probe of the probe card; and determining a characteristic of the test structure based on the input signal and the output signal.

公开(公告)号：US10790039B1

公开(公告)日：2020-09-29

申请号：US16584520

申请日：2019-09-26

申请人： MICRON TECHNOLOGY, INC.

发明人： Hyunui Lee ,  Chiaki Dono

IPC分类号： G11C29/02 ,  G11C29/12 ,  G11C29/48 ,  H01L23/48 ,  H01L23/498 ,  H01L27/108 ,  G11C29/30 ,  G11C29/56 ,  G11C29/44

摘要： Disclosed herein is an apparatus that includes a first semiconductor chip including a data I/O terminal, a test terminal, a first data input node, a first data output node, a read circuit, a write circuit, and a test circuit configured to transfer a test data supplied from the test terminal to the read circuit, and a second semiconductor chip including a second data input node connected to the first data output node, a second data output node connected to the first data input node, and a memory cell array. The test circuit is configured to activate the read circuit, the write circuit and the memory cell array so that the test data is written into the memory cell array via the read circuit, the data I/O terminal, the write circuit, the first data output node, and the second data input node.

公开(公告)号：US10679721B2

公开(公告)日：2020-06-09

申请号：US16046869

申请日：2018-07-26

申请人： Yangtze Memory Technologies Co., Ltd.

发明人： Jong Jun Kim ,  Feng Pan ,  Jong Seuk Lee ,  Zhenyu Lu ,  Yongna Li ,  Lidong Song ,  Youn Cheul Kim ,  Steve Weiyi Yang ,  Simon Shi-Ning Yang

IPC分类号： G11C29/00 ,  G11C29/50 ,  G11C29/48 ,  H01L27/11526 ,  H01L27/11573 ,  G11C29/02 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582 ,  H01L27/11578 ,  G11C29/12 ,  G11C29/56 ,  H01L27/11551 ,  G11C29/04

摘要： Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.

公开(公告)号：US10566266B2

公开(公告)日：2020-02-18

申请号：US15902913

申请日：2018-02-22

申请人： SK hynix Inc.

发明人： Heat Bit Park ,  Ji Hwan Kim ,  Dong Uk Lee

IPC分类号： H01L23/48 ,  G11C29/48 ,  H01L23/485 ,  G11C5/04 ,  H01L23/31 ,  G11C29/12

摘要： A semiconductor device includes a plurality of stacked chips is disclosed. Each of the stacked chips includes a plurality of through vias arranged in a regular polygonal shape. The through vias of each chip are formed at corresponding positions in a stacked direction. The respective through vias of each chip are electrically connected to through vias of a chip adjacent in the stacked direction in a manner that the connected through vias are spaced apart from one another in substantially the same direction.

公开(公告)号：US10559374B2

公开(公告)日：2020-02-11

申请号：US15436880

申请日：2017-02-20

申请人： Piecemakers Technology, Inc.

发明人： Gyh-Bin Wang ,  Chun-Kai Wang

IPC分类号： G11C29/12 ,  G11C29/36 ,  G11C29/48 ,  G11C29/54

摘要： A memory chip architecture includes a plurality of test pads, a plurality of interface pads, a function block and an embedded test block. The function block is coupled to the interface pads. The embedded test block is coupled to the test pads. The embedded test block is connected to an access port physical layer (PHY) through the interface pads. The interface pads are disposed between the function block and the embedded test block. The embedded test block is arranged for generating at least one test pattern as a test signal, and outputting the test signal to the function block through the interface pads to test the function block.

公开(公告)号：US10529438B2

公开(公告)日：2020-01-07

申请号：US15955076

申请日：2018-04-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ting-Shuo Hsu ,  Chih-Wei Shen

IPC分类号： G11C29/48

摘要： The present disclosure provides a dynamic random access device (DRAM). The DRAM includes a first node, a second node and a pad. The first node is configured to conduct a first internal signal generated by internal devices of the DRAM. The second node is configured to conduct a second internal signal generated by other internal devices of the DRAM. The pad is configured to receive one of the first internal signal and the second internal signal.