公开(公告)号：US20220328325A1

公开(公告)日：2022-10-13

申请号：US17850643

申请日：2022-06-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Alexander KALNITSKY ,  Wei-Cheng WU ,  Harry-Hak-Lay CHUANG

IPC分类号： H01L21/321 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

摘要： A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

公开(公告)号：US20200161319A1

公开(公告)日：2020-05-21

申请号：US16584710

申请日：2019-09-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei-Cheng WU ,  Chien-Hung CHANG

IPC分类号： H01L27/11524 ,  H01L29/788 ,  H01L29/66

摘要： A memory device includes a substrate, a transistor, and a memory cell. The substrate includes a cell region and a logic region. The transistor is over the logic region and includes a first metal gate stack. The memory cell is over the cell region and includes an erase gate. The erase gate is a metal gate stack.

公开(公告)号：US20190131249A1

公开(公告)日：2019-05-02

申请号：US16231735

申请日：2018-12-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Cheng-Hsien HSIEH ,  Li-Han HSU ,  Wei-Cheng WU ,  Hsien-Wei CHEN ,  Der-Chyang YEH ,  Chi-Hsi WU

IPC分类号： H01L23/544 ,  H01L23/528 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31

摘要： A method for forming a package structure and method for forming the same are provided. The method includes forming a package layer over a substrate, and forming a first dielectric layer over the package layer. The method further includes forming a first alignment mark and a second alignment mark over the first dielectric layer. The method includes forming a second dielectric layer over the first dielectric layer and removing a portion of the second dielectric layer to form a first trench to expose the first alignment mark, and to form a first opening to expose the second alignment.

公开(公告)号：US20170178719A1

公开(公告)日：2017-06-22

申请号：US15336633

申请日：2016-10-27

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei-Cheng WU ,  Chih-Yu LIN ,  Kao-Cheng LIN ,  Wei-Min CHAN ,  Yen-Huei CHEN

IPC分类号： G11C11/419

CPC分类号： G11C11/419

摘要： A device is disclosed that includes first memory cells, second memory cells, a first conductive line and a second conductive line. The first conductive line is electrically disconnected from the second conductive line. The first conductive line receives a first power voltage for the plurality of first memory cells. The second conductive line receives a second power voltage that is independent from the first power voltage, for the plurality of second memory cells.

公开(公告)号：US20150280004A1

公开(公告)日：2015-10-01

申请号：US14229191

申请日：2014-03-28

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Chang-Ming WU ,  Wei-Cheng WU ,  Yuan-Tai TSENG ,  Shih-Chang LIU ,  Chia-Shiung TSAI ,  Ru-Liang LEE ,  Harry Hak-Lay CHUANG

IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/49 ,  H01L29/66

CPC分类号： H01L27/11521 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28273 ,  H01L21/31111 ,  H01L21/32055 ,  H01L21/32133 ,  H01L21/32137 ,  H01L21/768 ,  H01L23/528 ,  H01L23/53271 ,  H01L23/5329 ,  H01L29/42328 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/6656 ,  H01L29/66825 ,  H01L29/7883 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.

摘要翻译： 提供嵌入高级逻辑电路中的非易失性存储器及其形成方法。 在非易失性存储器中，字线和擦除栅极的顶表面比控制栅极的顶表面低。 此外，在进行自对准硅化处理之前，字线和擦除栅极被电介质材料包围。 因此，在后续的化学机械抛光工艺中，字线和擦除栅极上不会形成金属硅化物，从而产生短路和漏电的问题。

公开(公告)号：US20150085556A1

公开(公告)日：2015-03-26

申请号：US14032222

申请日：2013-09-20

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Wei Min CHAN ,  Wei-Cheng WU ,  Yen-Huei CHEN

IPC分类号： G11C5/06 ,  H01L27/11 ,  G11C11/412

CPC分类号： G11C11/419 ,  G11C5/025 ,  G11C8/08 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0688 ,  H01L27/1104 ,  H01L2224/48227 ,  H01L2224/73265

摘要： A three dimensional dual-port bit cell generally comprises a first portion disposed on a first tier, wherein the first portion includes a plurality of port elements. The dual-port bit cell also includes a second portion disposed on a second tier that is vertically stacked with respect to the first tier using at least one via, wherein the second portion includes a latch.

摘要翻译： 三维双端口位单元通常包括设置在第一层上的第一部分，其中第一部分包括多个端口元件。 双端口位单元还包括设置在使用至少一个通孔相对于第一层垂直堆叠的第二层上的第二部分，其中第二部分包括闩锁。

公开(公告)号：US20240170551A1

公开(公告)日：2024-05-23

申请号：US18430522

申请日：2024-02-01

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Meng-Han LIN ,  Wei-Cheng WU ,  Te-Hsin CHIU

IPC分类号： H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

CPC分类号： H01L29/42368 ,  H01L21/02244 ,  H01L29/40117 ,  H01L29/42344 ,  H01L29/66833 ,  H01L29/792 ,  H10B43/35 ,  H10B43/40

摘要： A semiconductor device includes a semiconductor substrate, a control gate, a select gate, a charge trapping structure, a dielectric structure, and a spacer. The control gate and the select gate are over a channel region of the semiconductor substrate and separated from each other. The charge trapping structure is between the control gate and the semiconductor substrate. The dielectric structure is between the select gate and the semiconductor substrate. The dielectric structure has a first part and a second part, the first part is between the charge trapping structure and the second part, and the second part is thicker than the first part. The select gate is between the spacer and the control gate, and the select gate is separated from the spacer by the second part of the dielectric structure.

公开(公告)号：US20210217892A1

公开(公告)日：2021-07-15

申请号：US16743926

申请日：2020-01-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Wei-Cheng WU ,  Chih-Ren HSIEH

IPC分类号： H01L29/788 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L21/265 ,  H01L21/285 ,  H01L21/28 ,  H01L29/66

摘要： A memory device includes a semiconductor fin, a floating gate, a control gate, a source region, an erase gate, and a select gate. The floating gate is above and conformal to the semiconductor fin. The control gate is above the floating gate. The source region is in the semiconductor fin. The erase gate is above the source region and adjacent the control gate. The select gate is above the semiconductor fin. The control gate is between the erase gate and the select gate.

公开(公告)号：US20200279857A1

公开(公告)日：2020-09-03

申请号：US16875934

申请日：2020-05-15

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Harry-Hak-Lay CHUANG ,  Wei-Cheng WU ,  Ya-Chen KAO

IPC分类号： H01L27/11568 ,  H01L29/66 ,  H01L27/11573

摘要： A memory device includes a semiconductor substrate, a select gate stack, a main gate, a charge trapping layer, and a spacer. The a select gate stack is over the semiconductor substrate. The main gate is over the semiconductor substrate. The charge trapping layer has a first portion between the main gate and the semiconductor substrate. The spacer is on a sidewall of the main gate. At least a portion of the main gate is between the spacer and the select gate stack, and a lowermost surface of the spacer is above a lowermost surface of the main gate.

公开(公告)号：US20150145022A1

公开(公告)日：2015-05-28

申请号：US14092912

申请日：2013-11-27

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Harry Hak-Lay CHUANG ,  Wei-Cheng WU ,  Chang-Ming WU ,  Shih-Chang LIU

IPC分类号： H01L29/792 ,  H01L29/66

CPC分类号： H01L27/11573

摘要： A semiconductor device includes a substrate, at least one logic device and a split gate memory device. The at least one logic device is located on the substrate. The split gate memory device is located on the substrate and comprises a memory gate and a select gate. The memory gate and the select gate are adjacent to and electrically isolated with each other. A top of the select gate is higher than a top of the memory gate.

摘要翻译： 半导体器件包括衬底，至少一个逻辑器件和分离栅极存储器件。 至少一个逻辑器件位于衬底上。 分离栅极存储器件位于衬底上并且包括存储器栅极和选择栅极。 存储器栅极和选择栅极彼此相邻并且电隔离。 选择栅极的顶部高于存储器栅极的顶部。