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    HAMMING-DISTANCE ANALYZER AND METHOD FOR ANALYZING HAMMING-DISTANCE
    5.
    发明申请
    HAMMING-DISTANCE ANALYZER AND METHOD FOR ANALYZING HAMMING-DISTANCE 审中-公开

    公开(公告)号：US20180301204A1

    公开(公告)日：2018-10-18

    申请号：US16011215

    申请日：2018-06-18

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Shih-Lien Linus LU ,  Kun-Hsi LI ,  Saman M.I. ADHAM

    IPC: G11C29/56 ,  G11C29/38 ,  G11C29/14

    Abstract: A device is disclosed for testing a memory, and the memory includes a first memory circuit and a second memory circuit. The second memory circuit is configured to store a first response of the first memory circuit. The device includes a comparing circuit and a calculating circuit. The comparing circuit is configured to compare the first response stored in the second memory circuit with a plurality of responses of the first memory circuit operated in conditions that are different from each other, to generate a plurality of first comparing results. The calculating circuit is configured to output, according to the plurality of first comparing results, a maximum hamming distance between two of the first responses and the plurality of responses of the first memory circuit.

    METHOD AND APPARATUS FOR INTERCONNECT TEST
    6.
    发明申请
    METHOD AND APPARATUS FOR INTERCONNECT TEST 审中-公开
    用于互连测试的方法和装置

    公开(公告)号：US20160259006A1

    公开(公告)日：2016-09-08

    申请号：US15156140

    申请日：2016-05-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sandeep Kumar GOEL ,  Saman M.I. ADHAM

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/28

    CPC classification number: G01R31/31717 ,  G01R31/2856 ,  G01R31/3177 ,  G11C29/50

    Abstract: A test circuitry for testing an interconnection between interconnected dies includes a cell embedded within one of the dies. The cell includes a selection logic module that includes a first multiplexer configured to receive a first control signal and provide a first output test signal, and a second multiplexer configured to receive a second control signal and provide a second output test signal. The cell includes a scannable data storage module coupled to the first multiplexer; and a transition generation module configured to receive a third control signal; wherein the first and second output test signals are generated based on respective states of the first, second, and third control signals, and wherein the test circuitry is configured to use the first and second output test signals to perform at least two of: a DC test on the interconnection, an AC test on the interconnection, and a burn-in-test on the interconnection.

    Abstract translation: 用于测试相互连接的管芯之间的互连的测试电路包括嵌入在一个管芯内的电池。 小区包括选择逻辑模块，其包括被配置为接收第一控制信号并提供第一输出测试信号的第一多路复用器，以及被配置为接收第二控制信号并提供第二输出测试信号的第二多路复用器。 该小区包括耦合到第一多路复用器的可扫描数据存储模块; 以及转换生成模块，被配置为接收第三控制信号; 其中所述第一和第二输出测试信号是基于所述第一，第二和第三控制信号的相应状态生成的，并且其中所述测试电路被配置为使用所述第一和第二输出测试信号来执行以下至少两个：DC 互连测试，互连交流测试和互连上的老化测试。

    SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS
    7.
    发明申请
    SCAN ARCHITECTURE FOR INTERCONNECT TESTING IN 3D INTEGRATED CIRCUITS 有权

    公开(公告)号：US20230113905A1

    公开(公告)日：2023-04-13

    申请号：US18080680

    申请日：2022-12-13

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Sandeep Kumar GOEL ,  Yun-Han LEE ,  Saman M.I. ADHAM ,  Marat GERSHOIG

    IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/28 ,  G01R31/317

    Abstract: In one embodiment, a device comprises: a first die having disposed thereon a first plurality of latches wherein ones of the first plurality of latches are operatively connected to an adjacent one of the first plurality of latches; and a second die having disposed thereon a second plurality of latches wherein ones of the second plurality of latches are operatively connected to an adjacent one of the second plurality of latches. Each latch of the first plurality of latches on said first die corresponds to a latch in the second plurality of latches on said second die. Each set of corresponding latches are operatively connected. A scan path comprises a closed loop comprising each of said first and second plurality of latches. One of the second plurality of latches is operatively connected to another one of the second plurality of latches via an inverter.

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