公开(公告)号：US12116697B2

公开(公告)日：2024-10-15

申请号：US17773475

申请日：2020-12-24

Applicant: TOKUYAMA CORPORATION

Inventor： Toru Nagashima

IPC: C30B29/40 ,  C30B25/20 ,  C30B33/00 ,  H01L21/02

CPC classification number: C30B29/403 ,  C30B25/20 ,  C30B33/00 ,  H01L21/02024 ,  H01L21/02389 ,  H01L21/0254

Abstract: A group III nitride single crystal substrate comprises: a first main face; and a first back face opposite to the first main face, wherein an absolute value of a radius of curvature of the first main face of the substrate is 10 m or more; an absolute value of a radius of curvature of a crystal lattice plane at a center of the first main face of the substrate is 10 m or more; and a 1/1000 intensity width of an X-ray rocking curve of a low-incidence-angle face at the center of the first main face of the substrate is 1200 arcsec or less.

公开(公告)号：US20240297201A1

公开(公告)日：2024-09-05

申请号：US18609373

申请日：2024-03-19

Applicant: SUMCO Corporation

Inventor： Takeshi Kadono ,  Kazunari Kurita

IPC: H01L27/146 ,  C23C14/48 ,  C30B25/18 ,  C30B25/20 ,  C30B29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/322 ,  H01L29/167 ,  H01L29/36

CPC classification number: H01L27/14687 ,  C23C14/48 ,  C30B25/186 ,  C30B25/20 ,  C30B29/06 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/02658 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/3221 ,  H01L27/14689 ,  H01L29/167 ,  H01L29/36

Abstract: Provided is a semiconductor epitaxial wafer having metal contamination reduced by achieving higher gettering capability, a method of producing the semiconductor epitaxial wafer, and a method of producing a solid-state image sensing device using the semiconductor epitaxial wafer. The method of producing a semiconductor epitaxial wafer 100 includes a first step of irradiating a semiconductor wafer 10 containing at least one of carbon and nitrogen with cluster ions 16 thereby forming a modifying layer 18 formed from a constituent element of the cluster ions 16 contained as a solid solution, in a surface portion of the semiconductor wafer 10; and a second step of forming a first epitaxial layer 20 on the modifying layer 18 of the semiconductor wafer 10.

公开(公告)号：US20240271321A1

公开(公告)日：2024-08-15

申请号：US18693491

申请日：2022-09-13

Applicant: Soitec

Inventor： Frédéric Allibert ,  Eric Guiot

IPC: C30B25/20 ,  C30B28/14 ,  C30B29/36

CPC classification number: C30B25/20 ,  C30B28/14 ,  C30B29/36

Abstract: A method of fabricating a composite structure includes providing a c-SiC initial substrate, depositing a relatively thin p-SiC first layer on a front side of the initial substrate at a relatively high temperature, the first layer having a dopant concentration greater than 1019/cm3, forming a buried brittle plane in the initial substrate delineating a thin layer of single crystal SiC between the brittle plane and a front side of the initial substrate, depositing a relatively thick amorphous and/or polycrystalline SiC second layer on the first layer at a relatively low temperature, the second layer including dopants of the same type as those of the first layer, at a concentration greater than 1019/cm3, and depositing a p-SiC third layer on the second layer at a relatively high temperature. A separation along the buried brittle plane takes place during the deposition process.

公开(公告)号：US12054849B2

公开(公告)日：2024-08-06

申请号：US17630553

申请日：2020-06-10

Applicant: Byunggeun Ahn ,  Jae Hak Lee

Inventor： Hyung Soo Ahn ,  Jae Hak Lee

IPC: C30B25/14 ,  C23C16/24 ,  C23C16/30 ,  C23C16/448 ,  C23C16/455 ,  C23C16/458 ,  C30B25/10 ,  C30B25/12 ,  C30B25/16 ,  C30B25/20 ,  C30B29/06 ,  C30B29/40 ,  C30B29/66

CPC classification number: C30B25/14 ,  C23C16/24 ,  C23C16/303 ,  C23C16/4488 ,  C23C16/45512 ,  C23C16/4583 ,  C30B25/10 ,  C30B25/12 ,  C30B25/16 ,  C30B25/20 ,  C30B29/06 ,  C30B29/403 ,  C30B29/66

Abstract: An apparatus for manufacturing hexagonal Si crystal includes: a reaction tube; a mixed source part placed on one side in the reaction tube, for receiving mixed source of silicon, aluminum, and gallium which are in a solid state; a halogenation reaction gas supply pipe for supplying a halogenation reaction gas to the mixed source part; a substrate mounting part placed on the other side in the reaction tube, for mounting a first substrate, wherein the first substrate is disposed such that a crystal growth surface of the first substrate faces downwards; a nitrification reaction gas supply pipe for supplying a nitrification reaction gas to the substrate mounting part; and a heater for heating the reaction tube. The heater heats the reaction tube in a temperature range of 1100-1300° C.

公开(公告)号：US20240183066A1

公开(公告)日：2024-06-06

申请号：US18072931

申请日：2022-12-01

Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.

Inventor： Jeremy B. Reeves ,  Kevin T. Zawilski ,  Peter G. Schunemann

IPC: C30B25/20 ,  C09D5/00 ,  C30B25/16 ,  C30B29/42 ,  H05K9/00

CPC classification number: C30B25/20 ,  C09D5/006 ,  C30B25/16 ,  C30B29/42 ,  H05K9/0005 ,  H05K9/0094

Abstract: A method of manufacturing a structurally competent, EMI-shielded IR window includes using a mathematical model that combines the Sotoodeh and Nag models to determine an optimal thickness and dopant concentration of a doped layer of GaAs or GaP. A slab of GaAs or GaP is prepared, and a doped layer of the same material having the optimal thickness and dopant concentration is applied thereto. In embodiments, the doped layer is applied by an HVPE method such as LP-HVPE, which can also provide enhanced GaAs transparency near 1 micron. The Drude model can be applied to assist in selecting an anti-reflective coating. If the model predicts that the requirements of an application cannot be met by a doped layer alone, a doped layer can be applied that exceeds the required IR transparency, and a metallic grid can be applied to improve the EMI shielding, thereby satisfying the requirements.

公开(公告)号：US11987901B2

公开(公告)日：2024-05-21

申请号：US17711691

申请日：2022-04-01

Applicant: GlobalWafers Co., Ltd.

Inventor： Pietro Valcozzena ,  Maria Porrini ,  Januscia Duchini

IPC: C30B29/06 ,  C30B15/00 ,  C30B15/04 ,  C30B15/14 ,  C30B15/20 ,  C30B29/66 ,  C30B25/10 ,  C30B25/20

CPC classification number: C30B29/06 ,  C30B15/007 ,  C30B15/04 ,  C30B15/14 ,  C30B15/203 ,  C30B29/66 ,  C30B25/10 ,  C30B25/20

Abstract: Methods for preparing single crystal silicon substrates for epitaxial growth are disclosed. The methods may involve control of the (i) a growth velocity, v, and/or (ii) an axial temperature gradient, G, during the growth of an ingot segment such that v/G is less than a critical v/G and/or is less than a value of v/G that depends on the boron concentration of the ingot. Methods for preparing epitaxial wafers are also disclosed.

公开(公告)号：US11948794B2

公开(公告)日：2024-04-02

申请号：US17241903

申请日：2021-04-27

Applicant: Mitsubishi Electric Corporation

Inventor： Masashi Sakai ,  Takuma Mizobe ,  Takuyo Nakamura

IPC: H01L21/02 ,  C23C16/02 ,  C23C16/32 ,  C30B25/18 ,  C30B25/20 ,  C30B29/36 ,  H01L21/3065

CPC classification number: H01L21/02529 ,  C23C16/0236 ,  C23C16/325 ,  C30B25/186 ,  C30B25/20 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02634 ,  H01L21/3065

Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.

公开(公告)号：US20240047207A1

公开(公告)日：2024-02-08

申请号：US17879460

申请日：2022-08-02

Applicant: Infineon Technologies AG

Inventor： Christian Zmoelnig ,  Tobias Franz Wolfgang Hoechbauer ,  Andreas Voerckel ,  Hans Weber

IPC: H01L21/02 ,  H01L29/04 ,  H01L29/16 ,  H01L29/778 ,  C30B25/20 ,  C30B23/02 ,  C30B29/36 ,  C30B29/68

CPC classification number: H01L21/02609 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/7786 ,  C30B25/20 ,  C30B23/025 ,  C30B29/36 ,  C30B29/68

Abstract: A method of forming a semiconductor device includes providing a base substrate comprising SiC and a growth surface extending along a plane that is angled relative to a first crystallographic plane of the SiC from the base substrate, forming first and second trenches in the base substrate that extend from the growth surface into the base substrate, epitaxially forming a first SiC layer on the growth surface of the base substrate by a step-controlled epitaxy technique, and epitaxially forming a second SiC layer on the first SiC layer, wherein the first SiC layer is a layer of α-SiC, and wherein the second SiC layer is a layer of β-SiC.

公开(公告)号：US20240006243A1

公开(公告)日：2024-01-04

申请号：US17857018

申请日：2022-07-03

Applicant: ThinSIC Inc

Inventor： Tirunelveli Subramaniam Ravi ,  Stephen Daniel Miller ,  Jeffrey Scott Pietkiewicz ,  Kelly Marie Moyers

IPC: H01L21/78 ,  H01L29/16 ,  H01L29/872 ,  H01L21/02 ,  H01L29/66 ,  C30B33/02 ,  C30B25/04 ,  C30B25/20 ,  C30B29/36

CPC classification number: H01L21/7813 ,  H01L29/1608 ,  H01L29/872 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L29/6606 ,  C30B33/02 ,  C30B25/04 ,  C30B25/20 ,  C30B29/36

Abstract: A semiconductor substrate comprising a first epitaxial silicon carbide layer and a second silicon carbide epitaxial layer. At least one semiconductor device is formed in or on the second silicon carbide epitaxial layer. The semiconductor substrate is formed overlying a silicon carbide substrate having a surface comprising silicon carbide and carbon. An exfoliation process is used to remove the semiconductor substrate from the silicon carbide substrate. The carbon on the surface of the silicon carbide substrate supports separation. A portion of the silicon carbide substrate on the semiconductor substrate is removed after the exfoliation process. The surface of the silicon carbide substrate is prepared for reuse in subsequent formation of semiconductor substrates.

公开(公告)号：US11846040B2

公开(公告)日：2023-12-19

申请号：US17123338

申请日：2020-12-16

Applicant: DENSO CORPORATION ,  CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRY

Inventor： Yuichiro Tokuda ,  Hideyuki Uehigashi ,  Norihiro Hoshino ,  Hidekazu Tsuchida ,  Isaho Kamata

IPC: C30B29/36 ,  C30B25/20 ,  C01B32/956

CPC classification number: C30B29/36 ,  C30B25/20 ,  C01B32/956

Abstract: A silicon carbide single crystal contains a heavy metal element having a specific gravity higher than a specific gravity of iron. An addition density of the heavy metal element at least in an outer peripheral portion of the silicon carbide single crystal is set to 1×1015 cm−3 or more.