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    Electro-migration barrier for interconnect
    1.
    发明授权
    Electro-migration barrier for interconnect 有权

    公开(公告)号：US11515255B2

    公开(公告)日：2022-11-29

    申请号：US17104534

    申请日：2020-11-25

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Su-Jen Sung ,  Chih-Chiang Chang ,  Chia-Ho Chen

    IPC: H01L23/532 ,  H01L21/768

    Abstract: The present disclosure relates to an integrated circuit having a conductive interconnect disposed on a dielectric over a substrate. A first liner is arranged along an upper surface of the conductive interconnect. A barrier layer is arranged along a lower surface of the conductive interconnect and contacts an upper surface of the dielectric. The barrier layer and the first liner surround the conductive interconnect. A second liner is located over the first liner and has a lower surface contacting the upper surface of the dielectric.

    On-chip oscilloscope
    2.
    发明授权
    On-chip oscilloscope 有权

    公开(公告)号：US11035886B2

    公开(公告)日：2021-06-15

    申请号：US16212090

    申请日：2018-12-06

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Chung-Chieh Yang

    IPC: G01R19/00 ,  G01R13/00 ,  G01R13/02 ,  G01R31/28 ,  G01R31/317

    Abstract: A device is disclosed that includes a control circuit and a scope circuit. The control circuit is configured to delay a voltage signal to generate a first control signal. The scope circuit is configured to be operated in one of a first mode and a second mode according to the first control signal. In the first mode, the scope circuit is configured to generate a first current signal indicating amplitudes of the voltage signal, and in the second mode, the scope circuit is configured to stop generating the first current signal.

    ELECTRO-MIGRATION BARRIER FOR CU INTERCONNECT
    3.
    发明申请
    ELECTRO-MIGRATION BARRIER FOR CU INTERCONNECT 审中-公开

    公开(公告)号：US20190148308A1

    公开(公告)日：2019-05-16

    申请号：US16227062

    申请日：2018-12-20

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Su-Jen Sung ,  Chih-Chiang Chang ,  Chia-Ho Chen

    IPC: H01L23/532 ,  H01L21/768

    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated circuit device. The method may be performed by forming a conductive line over a substrate and in contact with a liner. A dielectric barrier layer is formed on the conductive line. The dielectric barrier layer includes an interfacial layer contacting the conductive line, a middle layer contacting the interfacial layer, and an upper layer contacting the middle layer. The interfacial layer and the liner collectively completely surround the conductive line. An inter-level dielectric layer is formed along sidewalls of the upper layer.

    Electro-Migration Barrier for Cu Interconnect
    4.
    发明申请
    Electro-Migration Barrier for Cu Interconnect 有权
    Cu互连电迁移屏障

    公开(公告)号：US20140264874A1

    公开(公告)日：2014-09-18

    申请号：US13967596

    申请日：2013-08-15

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Su-Jen Sung ,  Chih-Chiang Chang ,  Chia-Ho Chen

    IPC: H01L23/532 ,  H01L21/768

    CPC classification number: H01L23/53238 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Integrated circuit devices and method of forming them. The devices include a dielectric barrier layer formed over a copper-containing metal interconnect structure. The dielectric barrier layer inhibits electro-migration of Cu. The dielectric barrier layer includes a metal-containing layer that forms an interface with the interconnect structure. Incorporating metal within the interfacial layer improves adhesion of the dielectric barrier layer to copper lines and the like and provides superior electro-migration resistance over the operating lifetime of the devices.

    Abstract translation: 集成电路器件及其形成方法。 这些器件包括在含铜金属互连结构之上形成的介电阻挡层。 介电阻挡层抑制Cu的电迁移。 电介质阻挡层包括与互连结构形成界面的含金属层。 将界面层内的金属掺入提高介电阻挡层对铜线等的粘附性，并且在器件的使用寿命内提供优异的耐电迁移性。

    SOURCE/DRAIN FORMATION WITH REDUCED SELECTIVE LOSS DEFECTS
    5.
    发明申请
    SOURCE/DRAIN FORMATION WITH REDUCED SELECTIVE LOSS DEFECTS 有权

    公开(公告)号：US20240387702A1

    公开(公告)日：2024-11-21

    申请号：US18789176

    申请日：2024-07-30

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chih-Chiang Chang ,  Ming-Hua Yu ,  Li-Li Su

    IPC: H01L29/66 ,  H01L21/20 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/417 ,  H01L29/78

    Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin in an n-type Fin Field-Effect (FinFET) region and a p-type FinFET region, respectively, forming a first dielectric fin and a second dielectric fin in the n-type FinFET region and the p-type FinFET region, respectively, forming a first epitaxy mask to cover the second semiconductor fin and the second dielectric fin, performing a first epitaxy process to form an n-type epitaxy region based on the first semiconductor fin, removing the first epitaxy mask, forming a second epitaxy mask to cover the n-type epitaxy region and the first dielectric fin, performing a second epitaxy process to form a p-type epitaxy region based on the second semiconductor fin, and removing the second epitaxy mask. After the second epitaxy mask is removed, a portion of the second epitaxy mask is left on the first dielectric fin.

    On-chip oscilloscope
    6.
    发明授权
    On-chip oscilloscope 有权

    公开(公告)号：US11835551B2

    公开(公告)日：2023-12-05

    申请号：US18069813

    申请日：2022-12-21

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Chung-Peng Hsieh ,  Chih-Chiang Chang ,  Chung-Chieh Yang

    IPC: G01R19/00 ,  G01R13/00 ,  G01R13/02 ,  G01R31/28 ,  G01R31/317

    CPC classification number: G01R13/00 ,  G01R13/0218 ,  G01R31/2851 ,  G01R31/31726

    Abstract: A device includes a control circuit, a scope circuit, a first logic gate and a second logic gate. The control circuit is configured to generate a first control signal according to a voltage signal and a delayed signal. The scope circuit is configured to generate a first current signal in response to the first control signal and the voltage signal. The first logic gate is configured to perform a first logical operation on the voltage signal and one of the voltage signal and the delayed signal to generate a second control signal. The second logical gate configured to perform a second logical operation on the second control signal and a test control signal to generate a second current signal.

    Source and drain epitaxy re-shaping
    8.
    发明授权
    Source and drain epitaxy re-shaping 有权

    公开(公告)号：US10727131B2

    公开(公告)日：2020-07-28

    申请号：US15625501

    申请日：2017-06-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kun-Mu Li ,  Chih-Chiang Chang ,  Wen-Chu Hsiao ,  Che-Yu Lin ,  Wei-Siang Yang

    IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L29/08 ,  H01L29/165 ,  H01L29/161 ,  H01L21/3065 ,  H01L29/78

    Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.

    Area optimized series gate layout structure for FINFET array
    9.
    发明授权
    Area optimized series gate layout structure for FINFET array 有权
    FINFET阵列的面积优化系列门极布局结构

    公开(公告)号：US08719759B1

    公开(公告)日：2014-05-06

    申请号：US13778403

    申请日：2013-02-27

    Applicant: Taiwan Semiconductor Manufacturing Co. Ltd.

    Inventor： Wen-Shen Chou ,  Chin-Hua Wen ,  Yung-Chow Peng ,  Chih-Chiang Chang

    IPC: G06F17/50

    CPC classification number: G06F17/5068

    Abstract: The present disclosure relates to a method of optimizing the area of series gate layout structures for FinFET devices. The method analyzes an integrated chip (IC) layout to determine a first gate material density along a first direction and to separately determine a second gate material density along a second direction based upon the first gate material density. A number of series gate stages for a FinFET (field effect transistor) device having a gate length along the second direction, is chosen based upon the second gate material density and one or more device performance parameters of the FinFET device. By analyzing the density of gate material in separate directions, the effective length of the gate of the FinFET can be increased without increasing the size of the transistor array.

    Abstract translation: 本公开内容涉及一种优化FinFET器件的串联栅极布局结构的面积的方法。 该方法分析集成芯片（IC）布局以确定沿着第一方向的第一栅极材料密度，并且基于第一栅极材料密度沿着第二方向单独地确定第二栅极材料密度。 基于FinFET器件的第二栅极材料密度和一个或多个器件性能参数来选择用于具有沿着第二方向的栅极长度的FinFET（场效应晶体管）器件的多个串联栅极级。 通过分析栅极材料在不同方向上的密度，可以增加FinFET的栅极的有效长度，而不增加晶体管阵列的尺寸。

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