公开(公告)号：US12073167B2

公开(公告)日：2024-08-27

申请号：US18163916

申请日：2023-02-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Lu ,  Chih-Chiang Chang ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Yung-Chow Peng ,  Yung-Shun Chen ,  Tai-Yi Chen ,  Nai Chen Cheng

IPC: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

CPC classification number: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

公开(公告)号：US11574104B2

公开(公告)日：2023-02-07

申请号：US17135565

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Lu ,  Chih-Chiang Chang ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Yung-Chow Peng ,  Yung-Shun Chen ,  Tai-Yi Chen ,  Nai Chen Cheng

IPC: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.