公开(公告)号：US20240405776A1

公开(公告)日：2024-12-05

申请号：US18326539

申请日：2023-05-31

Applicant: NVIDIA Corporation

Inventor： Stefan P. Sywyk ,  Lalit Gupta ,  Jesse Wang

IPC: H03K19/0185 ,  G06F30/36 ,  G11C8/08 ,  G11C8/10

Abstract: The disclosure introduces a level-shifter including a boost circuit that provides a “one-shot” pulse (a self-annihilating pulse) with the transitioning edge of the output signal. The pulse can be used to produce a faster output rise time and reduce the overall footprint of a level-shifter compared to conventional level-shifters. In one example the level-shifter includes: (1) input circuitry configured to receive one or more input signals from one or more input voltage domains, (2) output circuitry configured to provide an output signal, based on at least one of the one or more input signals, for an output voltage domain, wherein an operating voltage of the output voltage domain is greater than an operating voltage of the one or more input voltage domains, and (3) a boost circuit connected to the output circuitry and configured to provide a current pulse for a transition edge of the output signal.

公开(公告)号：US11763055B2

公开(公告)日：2023-09-19

申请号：US17317500

申请日：2021-05-11

Applicant: REZONENT CORPORATION

Inventor： Ignatius Bezzam

IPC: G06F30/00 ,  G06F30/35 ,  H03K19/096 ,  H03K19/00 ,  G06F30/36 ,  G06F30/327 ,  G06F119/06 ,  H03K5/15 ,  H02M7/48

CPC classification number: G06F30/35 ,  G06F30/327 ,  G06F30/36 ,  H03K19/0019 ,  H03K19/0963 ,  H03K19/0966 ,  G06F2119/06 ,  H02M7/4826 ,  H02P2201/05 ,  H03K5/15

Abstract: Reduced-power dynamic data circuits with wide-band energy recovery are described herein. In one embodiment, a circuit system comprises at least one sub-circuit in which at least one of the sub-circuits includes a capacitive output node that is driven between low and high states in a random manner for a time period and an inductive circuit path coupled to the capacitive output node. The inductive circuit path includes a transistor switch and an inductor connected in series to discharge and recharge the output node to a bias supply. A pulse generator circuit generates a pulse width that corresponds to a timing for driving the output node.

公开(公告)号：US11704448B2

公开(公告)日：2023-07-18

申请号：US17385505

申请日：2021-07-26

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F30/00 ,  G06F30/30 ,  G06F30/36 ,  G06F30/367

CPC classification number: G06F30/00 ,  G06F30/30 ,  G06F30/36 ,  G06F30/367

Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

公开(公告)号：US20230115495A1

公开(公告)日：2023-04-13

申请号：US17861362

申请日：2022-07-11

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： CHIEN-SHENG LEE

IPC: G06F30/36

Abstract: An impedance matching method includes following operations: providing load impedance data of a network interface controller chip; providing characteristic data of a network transformer, in which the network transformer is configured to be connected to the network interface controller chip via a transmission line on a printed circuit board, and a first predetermined data rate of the network transformer is lower than a second predetermined data rate of the network interface controller chip; adjusting an arrangement among the load impedance data, a length of the transmission line, and a width of the transmission line according to the characteristic data to adjust an impedance matching between the network transformer and the network interface controller chip, in order to make the network transformer meet a predetermined requirement corresponding to the second predetermined data rate; and storing the arrangement to be design data for fabricating the printed circuit board.

公开(公告)号：US11574104B2

公开(公告)日：2023-02-07

申请号：US17135565

申请日：2020-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Ting Lu ,  Chih-Chiang Chang ,  Chung-Peng Hsieh ,  Chung-Chieh Yang ,  Yung-Chow Peng ,  Yung-Shun Chen ,  Tai-Yi Chen ,  Nai Chen Cheng

IPC: G06F30/392 ,  G06F30/36 ,  G06F30/367 ,  G06F30/394

Abstract: An electronic design flow generates an electronic architectural design layout for analog circuitry from a schematic diagram. The electronic design flow assigns analog circuits of the schematic diagram to various categories of analog circuits. The electronic design flow places various analog standard cells corresponding to these categories of analog circuits into analog placement sites assigned to the analog circuits. These analog standard cells have a uniform cell height which allows these analog standard cells to be readily connected or merged to digital standard cells which decreases the area of the electronic architectural design layout. This uniformity in height between these analog standard cells additionally provides a more reliable yield when compared to non-uniform analog standard cells.

公开(公告)号：US20220407371A1

公开(公告)日：2022-12-22

申请号：US17776441

申请日：2020-11-13

Applicant: NIPPON STEEL CORPORATION

Inventor： Yasuo OHSUGI ,  Miho TOMITA ,  Tesshu MURAKAWA

IPC: H02K1/16 ,  H02K1/02 ,  C22C38/16 ,  C22C38/10 ,  C22C38/06 ,  C22C38/04 ,  C22C38/02 ,  C22C38/00 ,  G06F30/36

Abstract: The present invention is a stator core having a plurality of laminated electrical steel sheets, in which, among a plurality of teeth (121a to 121p) of the stator core, a width of teeth along a direction in which magnetic characteristics are excellent may be narrower than a width of teeth along a direction in which the magnetic characteristics are poor.

公开(公告)号：US11507124B2

公开(公告)日：2022-11-22

申请号：US16706039

申请日：2019-12-06

Applicant: Texas Instruments Incorporated

Inventor： Dien Mac ,  Satyanandakishore V. Vanapalli ,  Jeffrey Perry ,  Wanda C. Garrett ,  Jonathan J. Arzadon

IPC: G05F1/625 ,  G05F1/66 ,  G05B15/02 ,  G06F30/36 ,  G06F119/06

Abstract: A method (and system) includes receiving, at a computing device including a design tool application, design parameters indicative of a plurality of power supply loads to be powered. The method further includes generating power supply solutions that do not include multi-channel voltage regulators and generating power supply solutions that do include multi-channel voltage regulators. The method also includes ranking all power supply solutions and providing the ranked power supply solutions to a user.

公开(公告)号：US11467804B2

公开(公告)日：2022-10-11

申请号：US16457094

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Sergey Vladimirovich Gribok ,  Gregg William Baeckler ,  Martin Langhammer

IPC: G06F7/501 ,  G06F17/11 ,  G06F30/34 ,  G06F30/36

Abstract: A computer-implemented method for programming an integrated circuit includes receiving a program design and determining one or more addition operations based on the program design. The method also includes performing geometric synthesis based on the one or more addition operations by determining a plurality of bits associated with the one or more addition operations and defining a plurality of counters that includes the plurality of bits. Furthermore, the method includes generating instructions configured to cause circuitry configured to perform the one or more addition operations to be implemented on the integrated circuit based on the plurality of counters. The circuitry includes first adder circuitry configured to add a portion of the plurality of bits and produce a carry-out value. The circuitry also includes second adder circuitry configured to determine a sum of a second portion of the plurality of bits and the carry-out value.

公开(公告)号：US20220278099A1

公开(公告)日：2022-09-01

申请号：US17542014

申请日：2021-12-03

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Hui Chen ,  Tzu-Ching Chang ,  Weichih Chen ,  Wan-Te Chen ,  Tsung-Hsin Yu ,  Cheng-Hsiang Hsieh

IPC: H01L27/092 ,  G06F30/392 ,  G06F30/36 ,  G06F30/327

Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.

公开(公告)号：US20220156445A1

公开(公告)日：2022-05-19

申请号：US17471175

申请日：2021-09-10

Applicant: Baum Design Systems Co., Ltd.

Inventor： In Hak HAN

IPC: G06F30/36

Abstract: The present disclosure relates to a method of predicting power consumption of an integrated circuit. The method includes receiving a gate-level netlist of the integrated circuit, receiving a plurality of libraries defining operation of at least one cell included in the netlist, receiving signal switching information in the netlist, receiving a target corner including a target operating voltage (VDDtarg) and a target temperature (Ttarg), and estimating switching power at the target corner of the integrated circuit on the basis of the netlist, the signal switching information, and the target operating voltage (VDDtarg).