公开(公告)号：US09875325B2

公开(公告)日：2018-01-23

申请号：US14707723

申请日：2015-05-08

Applicant: ZIPALOG, INC.

Inventor： Felicia James ,  Michael Krasnicki

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5045 ,  G06F17/5063

Abstract: A computer implemented system and method of identification of useful untested states of an electronic design, comprising, parsing at least one netlist of a representation of the electronic design comprised at least in part of at least one analog portion, determining at least one instrumentation point based on the at least one netlist, generating at least one instrumented netlist based on the at least one instrumentation point and determining an analog verification coverage utilizing the at least one instrumented netlist.

公开(公告)号：US09536028B2

公开(公告)日：2017-01-03

申请号：US14788091

申请日：2015-06-30

Applicant: ZIPALOG, INC.

Inventor： Michael Krasnicki ,  Yue Deng

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5036 ,  G06F17/5063 ,  G06F17/5081

Abstract: A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature.

Abstract translation: 计算机实现电子设计变更评估的方法和系统，用于验证确认。 该方法具有以下步骤：接收包括子组件的电子设计，采用代表子组件的数据的银行签名，接收子组件的审查请求，生成代表子组件的数据的当前签名，并确定 当前签名和银行签名。

公开(公告)号：US09147026B2

公开(公告)日：2015-09-29

申请号：US14559583

申请日：2014-12-03

Applicant: ZIPALOG, INC.

Inventor： Michael Krasnicki ,  Yue Deng

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5036 ,  G06F17/5063 ,  G06F17/5081

Abstract: A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature.

公开(公告)号：US11704448B2

公开(公告)日：2023-07-18

申请号：US17385505

申请日：2021-07-26

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F30/00 ,  G06F30/30 ,  G06F30/36 ,  G06F30/367

CPC classification number: G06F30/00 ,  G06F30/30 ,  G06F30/36 ,  G06F30/367

Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

公开(公告)号：US10402505B2

公开(公告)日：2019-09-03

申请号：US15654469

申请日：2017-07-19

Applicant: ZIPALOG, INC.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F17/50

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netlist based at least in part upon the translation.

公开(公告)号：US10262093B2

公开(公告)日：2019-04-16

申请号：US15871210

申请日：2018-01-15

Applicant: ZIPALOG, INC.

Inventor： Felicia James ,  Michael Krasnicki

IPC: G06F17/50

Abstract: A computer implemented system and method of computer implemented method of instrumentation of an electronic design comprising receiving by a computer a computer readable representation of said electronic design having at least in one part of said electronic design, an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is received and at least one set of valid states is generated based on said at least one specification. An analog verification coverage is determined utilizing said at least one instrumented netlist.

公开(公告)号：US11657201B2

公开(公告)日：2023-05-23

申请号：US17316270

申请日：2021-05-10

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki

IPC: G06F30/367 ,  G06F30/30 ,  G06F30/36

CPC classification number: G06F30/367 ,  G06F30/30 ,  G06F30/36

Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a representation of said electronic design comprised at least in part of at least one analog portion, at least one specification of said electronic design, at least one manufacturing process variation of said at least one analog portion of said electronic design and at least one functional variation of said at least one analog portion of said electronic design. At least one set of valid states delimited by one of said at least one specification, said at least one manufacturing process variation and said at least one functional variation is then generated.

公开(公告)号：US11074373B2

公开(公告)日：2021-07-27

申请号：US16848282

申请日：2020-04-14

Applicant: Zipalog Inc.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F30/00 ,  G06F30/30 ,  G06F30/36 ,  G06F30/367

Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

公开(公告)号：US20200320242A1

公开(公告)日：2020-10-08

申请号：US16909411

申请日：2020-06-23

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki

IPC: G06F30/367 ,  G06F30/30 ,  G06F30/36

Abstract: A computer program product embodied on a non-transitory computer usable medium includes a sequence of instructions causing at least one processor to execute a method of identification of useful untested states of an electronic design. A computer receives a computer readable representation of said electronic design having at least in one part of said electronic design an analog portion. At least one instrumented netlist is generated based at least in part upon said representation of said electronic design. At least one specification of said electronic design is also received. At least one set of valid states are generated based on said at least one specification. The at least one instrumented netlist is simulated at a behavioral level of said representation of said electronic design at a minimum number of at least one input vector. At least one verification coverage history of said electronic design is generated based in part upon said simulation. Useful untested states are identified based at least in part upon at least one of said at least one specification, said at least one instrumented netlist, said at least one set of valid states and said at least one verification coverage history.

公开(公告)号：US08930877B1

公开(公告)日：2015-01-06

申请号：US13929007

申请日：2013-06-27

Applicant: Zipalog, Inc.

Inventor： Michael Krasnicki ,  Yue Deng

IPC: G06F17/50 ,  G06F11/22

CPC classification number: G06F17/5045 ,  G06F17/5036 ,  G06F17/5063 ,  G06F17/5081

Abstract: A computer implemented method and system of change evaluation of an electronic design for verification confirmation. The method has the steps of receiving the electronic design comprised a subcomponent, employing a banked signature of data representative of the subcomponent, receiving a review request of the subcomponent, generating a current signature of the data representative of the subcomponent and determining a difference of the current signature and the banked signature.

Abstract translation: 计算机实现电子设计变更评估的方法和系统，用于验证确认。 该方法具有以下步骤：接收包括子组件的电子设计，采用代表子组件的数据的银行签名，接收子组件的审阅请求，生成表示子组件的数据的当前签名，并确定 当前签名和银行签名。