公开(公告)号：US20150324505A1

公开(公告)日：2015-11-12

申请号：US14707689

申请日：2015-05-08

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F17/5022 ,  G06F17/5036 ,  G06F17/5045

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.

Abstract translation: 一种计算机实现的电子设计验证命令的翻译方法，包括以下步骤：接收电子设计，接收至少一个具有至少一个间接分支贡献语句的模拟测试线束模型，将至少一个间接分支贡献语句转换成 至少部分地基于所述至少一个模拟测试线束模型并且至少部分地基于所述翻译来生成网表的多个直接分支贡献运算符。

公开(公告)号：US11074373B2

公开(公告)日：2021-07-27

申请号：US16848282

申请日：2020-04-14

Applicant: Zipalog Inc.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F30/00 ,  G06F30/30 ,  G06F30/36 ,  G06F30/367

Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

公开(公告)号：US11704448B2

公开(公告)日：2023-07-18

申请号：US17385505

申请日：2021-07-26

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F30/00 ,  G06F30/30 ,  G06F30/36 ,  G06F30/367

CPC classification number: G06F30/00 ,  G06F30/30 ,  G06F30/36 ,  G06F30/367

Abstract: A computer implemented method of translation of verification commands of an electronic design file of an electronic circuit defined by the electronic design file, comprising receiving, at a processor, the electronic design file defining a functional level electronic design of the electronic circuit, wherein said electronic circuit comprises at least two subsystems and said electronic circuit includes at least two configuration options for the at least two subsystems, receiving along with the electronic design file, at least one analog test harness model having at least one indirect branch contribution statement, translating said at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon said at least one analog test harness model and said electronic design file and generating a netlist for the electronic circuit based at least in part upon said translation of said at least one indirect branch contribution statement.

公开(公告)号：US10402505B2

公开(公告)日：2019-09-03

申请号：US15654469

申请日：2017-07-19

Applicant: ZIPALOG, INC.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F17/50

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement and having at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and at least one of at least one stimulus parameter stored in at least one specification database and at least one measurement parameter stored in at least one specification database and at least one specification parameter stored in at least one specification database and generating a netlist based at least in part upon the translation.

公开(公告)号：US09715566B2

公开(公告)日：2017-07-25

申请号：US14707689

申请日：2015-05-08

Applicant: Zipalog, Inc.

Inventor： Felicia James ,  Michael Krasnicki ,  Xiyuan Wu

IPC: G06F17/50

CPC classification number: G06F17/5063 ,  G06F17/5022 ,  G06F17/5036 ,  G06F17/5045

Abstract: A computer implemented method of translation of verification commands of an electronic design, comprises the steps of receiving the electronic design, receiving at least one analog test harness model having at least one indirect branch contribution statement, translating the at least one indirect branch contribution statement into a plurality of direct branch contribution operators based at least in part upon the at least one analog test harness model and generating a netlist based at least in part upon the translation.