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公开(公告)号:US20250031443A1
公开(公告)日:2025-01-23
申请号:US18785647
申请日:2024-07-26
Inventor: Chung-Hui Chen , Tzu-Ching Chang , Weichih Chen , Wan-Te Chen , Tsung-Hsin Yu , Cheng-Hsiang Hsieh
IPC: H01L27/092 , G06F30/327 , G06F30/36 , G06F30/392 , G06F115/06 , G06F117/12
Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.
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公开(公告)号:US20220278099A1
公开(公告)日:2022-09-01
申请号:US17542014
申请日:2021-12-03
Inventor: Chung-Hui Chen , Tzu-Ching Chang , Weichih Chen , Wan-Te Chen , Tsung-Hsin Yu , Cheng-Hsiang Hsieh
IPC: H01L27/092 , G06F30/392 , G06F30/36 , G06F30/327
Abstract: An integrated circuit (IC) including a plurality of finfet cells designed with digital circuit design rules to provide smaller finfet cells with decreased cell heights, and analog circuit cell structures including first finfet cells of the plurality of finfet cells and including at least one cut metal layer. The smaller finfet cells with decreased cell heights provide a first shorter metal track in one direction and the at least one cut metal layer provides a second shorter metal track in another direction to increase maximum electromigration currents in the integrated circuit.
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公开(公告)号:US20240387518A1
公开(公告)日:2024-11-21
申请号:US18787569
申请日:2024-07-29
Inventor: Chung-Hui Chen , Wan-Te Chen , Shu-Wei Chung , Tung-Heng Hsieh , Tzu-Ching Chang , Tsung-Hsin Yu , Yung Feng Chang
IPC: H01L27/06 , H01L29/06 , H01L29/423 , H01L29/786
Abstract: A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.
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公开(公告)号:US12094872B2
公开(公告)日:2024-09-17
申请号:US17643651
申请日:2021-12-10
Inventor: Chung-Hui Chen , Wan-Te Chen , Shu-Wei Chung , Tung-Heng Hsieh , Tzu-Ching Chang , Tsung-Hsin Yu , Yung Feng Chang
IPC: H01L27/06 , H01L29/06 , H01L29/423 , H01L29/786
CPC classification number: H01L27/0629 , H01L29/0653 , H01L29/0673 , H01L29/42392 , H01L29/78696
Abstract: A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first and second nanosheet structures have at least one nanosheet forming source/drain regions and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure and the gate structure of the first nanosheet structure define a capacitor.
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公开(公告)号:US12068306B2
公开(公告)日:2024-08-20
申请号:US18312219
申请日:2023-05-04
Inventor: Chung-Hui Chen , Tzu-Ching Chang , Cheng-Hsiang Hsieh
IPC: H01L27/02 , G06F30/3953 , H01L23/522 , H01L23/528
CPC classification number: H01L27/0207 , G06F30/3953 , H01L23/5226 , H01L23/528
Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first transistor and a second transistor over the first side of the substrate, a first conductive pattern over the first side of the substrate, and a second conductive pattern under the second side of the substrate. The first conductive pattern electrically couples a first terminal of the first transistor to a second terminal of the second transistor. The second conductive pattern electrically couples the first terminal of the first transistor to the second terminal of the second transistor.
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公开(公告)号:US11676957B2
公开(公告)日:2023-06-13
申请号:US17189908
申请日:2021-03-02
Inventor: Chung-Hui Chen , Tzu-Ching Chang , Cheng-Hsiang Hsieh
IPC: H01L27/02 , G06F30/3953 , H01L23/528 , H01L23/522
CPC classification number: H01L27/0207 , G06F30/3953 , H01L23/528 , H01L23/5226
Abstract: An integrated circuit (IC) device includes a substrate having opposite first and second sides, an active region over the first side of the substrate, a first conductive pattern over the active region, and a second conductive pattern under the second side of the substrate. The active region includes a first portion and a second portion. The first conductive pattern is electrically coupled to the first portion and the second portion of the active region. The second conductive pattern is electrically coupled to the first portion and the second portion of the active region.
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